E.1.1.5 Xer Register (Xer) - Motorola MPC8240 User Manual

PowerPC Register Set
Table E-5 illustrates the floating-point result flags used by PowerPC processors. The result
flags correspond to FPSCR bits 15–19.
Table E-5. Floating-Point Result Flags in FPSCR

E.1.1.5 XER Register (XER)

The XER register (XER) is a 32-bit, user-level register shown in Figure E-6.
.
SO OV CA
0 1 2 3
The bit definitions for XER are shown in Table E-6.
Bit(s) Name
0 SO Summary overflow. The summary overflow bit (SO) is set whenever an instruction (except mtspr)
sets the overflow bit (OV). Once set, the SO bit remains set until it is cleared by an mtspr
instruction (specifying the XER) or an mcrxr instruction. It is not altered by compare instructions,
nor by other instructions (except mtspr to the XER, and mcrxr) that cannot overflow. Executing an
mtspr instruction to the XER, supplying the values zero for SO and one for OV, causes SO to be
cleared and OV to be set.
1 OV Overflow. The overflow bit (OV) is set to indicate that an overflow has occurred during execution of
an instruction. Add, subtract from, and negate instructions having OE = 1 set the OV bit if the carry
out of the msb is not equal to the carry out of the msb + 1, and clear it otherwise. Multiply low and
divide instructions having OE = 1 set the OV bit if the result cannot be represented in 64 bits
(mulld, divd, divdu) or in 32 bits (mullw, divw, divwu), and clear it otherwise. The OV bit is not
altered by compare instructions that cannot overflow (except mtspr to the XER, and mcrxr).
E-8
Result Flags (Bits 15–19)
C < > = ?
1 0 0 0 1
0 1 0 0 1
0 1 0 0 0
1 1 0 0 0
1 0 0 1 0
0 0 0 1 0
1 0 1 0 0
0 0 1 0 0
0 0 1 0 1
0 0000 0000 0000 0000 0000 0
Figure E-6. XER Register
Table E-6. XER Bit Definitions
MPC8240 Integrated Processor User's Manual
Result Value Class
Quiet NaN
–Infinity
–Normalized number
–Denormalized number
–Zero
+Zero
+Denormalized number
+Normalized number
+Infinity
Description
Reserved
Byte count
24 25 31