_
SDRAM
CLK[0:3]
ts
CKE
RAS/CS
SDRAS
SDCAS
CAS/DQM
ADDRESS
SDRAM
DATA
WE
DEBUG
ADDRESS
MIV
MAA
Figure 15-12. Example SDRAM Debug Address, MIV, and MAA Timings for Burst
ACTORW
ROW
CAS LATENCY
VALID
VALID
Read Operation
Chapter 15. Debug Features
Memory Interface Valid (MIV)
COL
D0
D1
D2
D3
ROW
15-13