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Table 6-13. The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 32:63)
Syndrome
3
3
3
3
Bit
2
3
4
5
0
x
1
x
2
x x x x x x x x x x x x x x x x
3
x
4
x x x
5
6
7
x x
6.2.11 SDRAM Registered DIMM Mode
The MPC8240 can be configured to support registered SDRAM DIMMs. To reduce
loading, registered DIMMs latch the SDRAM control signals internally before using them
to access the array. Enabling the MPC8240's registered DIMM mode (MCCR4 bit 15,
REGDIMM = 1) compensates for this delay on the DIMMs control bus by delaying the
MPC8240's data and parity buses for SDRAM writes by one additional clock cycle.
Enabling registered DIMM mode has no affect on the bus timing for SDRAM reads or
ROM/Flash transfers. However, the programmed read latency (RDLAT) time for SDRAM
reads must be incremented by one to compensate for the latch delay on the control signals
of the registered DIMM. Figure 6-15 shows the registered SDRAM DIMM single-beat
write timing.
3
3
3
3
4
4
4
4
4
6
7
8
9
0
1
2
3
4
x
x
x
x
x
x
x
x x x
x x x
x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x
x x x x
Chapter 6. MPC8240 Memory Interface
Data Bit
4
4
4
4
4
5
5
5
5
5
6
7
8
9
0
1
2
3
x
x
x x
x
x
x
x
x x x
x x x x x x x x
SDRAM Interface Operation
5
5
5
5
5
5
6
6
4
5
6
7
8
9
0
1
x
x
x
x
x
x
x
x x x x
x x x x
x x x x x x x x
x x x
6
6
2
3
x
x
6-29
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