Embedded Programmable Interrupt Controller (EPIC)
Signal Descriptions and Clocking
Configuration Registers
PowerPC Processor Core
MPC8240 Memory Interface
Programmable I/O and Watchpoint
Bit and Byte Ordering
PowerPC Instruction Set
P
Processor Core Register Summary
Glossary of Terms and Abbreviations
Overview
Address Maps
PCI Bus Interface
DMA Controller
Message Unit (I
2
I
C Interface
Central Control Unit
Error Handling
Power Management
Debug Features
Address Map A
Initialization Example
1
2
3
4
5
6
7
8
O)
9
2
10
11
12
13
14
15
15
16
A
B
C
D
E
GLO
Index
IND