Cache Implementation - Motorola MPC8240 User Manual

Cache Implementation

separate instructions. Decoupling computational instructions from memory accesses
increases throughput by facilitating pipelining.
PowerPC processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of several
components of the system software to be invoked.
5.3.2.3 MPC8240 Implementation-Specific Instruction Set
The MPC8240 processor core instruction set is defined as follows:
• The processor core provides hardware support for all 32-bit PowerPC instructions.
• The processor core provides two implementation-specific instructions used for
software table search operations following TLB misses:
— Load Data TLB Entry (tlbld)
— Load Instruction TLB Entry (tlbli)
• The processor core implements the following instructions defined as optional by the
PowerPC architecture:
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
— Store Floating-Point as Integer Word Indexed (stfiwx)
— External Control In Word Indexed (eciwx)
— External Control Out Word Indexed (ecowx)
The MPC8240 does not provide the hardware support for misaligned eciwx and ecowx
instructions provided by the MPC603e processor. An alignment exception is taken if these
instructions are not word-aligned.
5.4 Cache Implementation
The MPC8240 processor core has separate data and instruction caches. The cache
implementation is described in the following sections.
5.4.1 PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For
example, some PowerPC processors, including the MPC8240's processor core, have
separate instruction and data caches (Harvard architecture); others, such as the PowerPC
601® microprocessor implement a unified cache.
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