Dma Coherency - Motorola MPC8240 User Manual

DMA Operation

8.3.4 DMA Coherency

Each DMA channel contains a 64-byte transfer queue. No address snooping occurs in these
queues. It is possible that certain data could be posted in these queues and not be visible to
the rest of the system while a DMA transfer is in progress. Therefore, software must enforce
coherency of the region being transferred during the DMA process.
Snooping of the processor data cache is selectable during DMA transactions. A snoop bit
(SNEN) is provided in the CDAR and the next descriptor address register (NDAR) which
allows software to control whether the processor cache is snooped. This bit is described in
Section 8.7.3, "Current Descriptor Address Registers (CDARs)," and Section 8.7.8, "Next
Descriptor Address Registers (NDARs)," respectively.
The MPC8240 architecture assumes that all of the local or host memory is prefetchable
including Port X. Note that this results in multiple reads occurring to the same location on
the memory interface and Port X.
8.3.5 DMA Performance
The arbitration logic between the DMA controller and other PCI masters is clocked by the
PCI clock. However, the DMA controller operates on the memory bus clock, and it
communicates to local memory through the central control unit (CCU) that is also clocked
by the memory bus clock during transactions with the memory controller. This difference
in clocking introduces time delays between the time domains of the PCI devices and the
CCU. The phase of the PCI clock relative to the memory bus clock causes latency between
the time the DMA controller is programmed to start a transaction and the time the data is
actually returned.
Additionally, care must be taken when polling the DMA registers. Access to any of the
system registers (configuration and runtime registers) on the MPC8240 temporarily
interrupt a DMA stream. Thus, if the processor polls the DMA channel busy bit in the DSR
while a DMA transfer is in progress, the DMA transfer is temporarily interrupted, and the
performance of the DMA transfer is drastically reduced. To obtain the best performance,
the interrupt features of the DMA controller should be used for signalling conditions such
as channel complete to the processor.
DMA accesses to local memory may require cache coherency with the processor; such
accesses require snooping on the peripheral logic bus. However, snoop hits from the
peripheral logic bus (from the L1 cache) for DMA accesses degrade DMA performance. To
minimize this effect, the corresponding areas of memory in the processor cache(s) should
be flushed prior to initiating the DMA transfers. The arbitration priorities described in
Section 12.2, "Internal Arbitration," show the effect of snooping on the priorities for access
to the processor/memory data bus.
8-8 MPC8240 Integrated Processor User's Manual