I2Cadr Field Descriptions—Offset 0X0_3000 - Motorola MPC8240 User Manual

2
I C Register Descriptions
Table 10-3 describes the bit settings of I2CADR.
Table 10-3. I2CADR Field Descriptions—Offset 0x0_3000
Reset
Bits Name
Value
31–8 — All zeros
7–1 ADDR 0x00
0 — 0
2
10.3.2 I C Frequency Divider Register (I2CFDR)
The I2CFDR, shown in Figure 10-4, configures the sampling rate and the clock bit rate for
2
the I C unit.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31
Figure 10-4. I
Table 10-4 describes the bit settings of the I2CFDR.
Table 10-4. I2CFDR Field Descriptions—Offset 0x0_3004
Reset
Bits Name
Value
31–14 — All 0s
13–8 DFFSR 0x10
7–6 — 00
5–0 FDR 0x00
10-8
R/W
R Reserved
R/W Slave address. Contains the specific address to which the MPC8240
responds as a slave on the I
2
I C interface is slave mode for an address match.
R Reserved
2
C Frequency Divider Register (I2CFDR)
R/W
R Reserved
R/W Digital filter frequency sampling rate—To assist in filtering out signal noise, the
sample rate is programmable; this field is used to prescale the frequency at
which the digital filter takes samples from the I
rate is the local memory frequency (SDRAM_CLK) divided by the non-zero
value set in this field. If DFFSR is set to zero, the I
to the reset divisor 0x10.
R Reserved
R/W Frequency divider ratio—Used to prescale the clock for bit rate selection. The
serial bit clock frequency of SCL is equal to the local memory clock
(SDRAM_CLK) divided by the divider shown in Table 10-5. Note that the
frequency divider value can be changed at any point in a program.
MPC8240 Integrated Processor User's Manual
Description
2
C interface. Note that the default mode of the
DFFSR 0 0
14 13 8 7 6
Description
2
C bus. The resulting sampling
2
C bus sample points default
Reserved
FDR
5 0