Motorola MPC8240 User Manual page 630

IFQPR (inbound FIFO queue port) register, 9-11
IFTPR (inbound free_FIFO tail pointer) register, 9-16
ILR (PCI interrupt line) register, 4-16
IMIMR (inbound message interrupt mask)
register, 9-14
IMISR (inbound message interrupt status)
register, 9-12
Instructions
branch instructions, D-24
cache management instructions, D-25
condition register logical, D-24
external control, D-26
floating-point
arithmetic, D-19
compare, D-20
FP load instructions, D-23
FP move instructions, D-23
FP store instructions, D-23
FPSCR isntructions, D-20
multiply-add, D-20
rounding and conversion, D-20
instruction timing overview, 5-32
instruction unit, 5-5
integer
arithmetic, D-17
compare, D-18
load, D-21
logical, D-18
multiple, D-22
rotate and shift, D-18–D-19
store, D-21
load and store
byte-reverse instructions, D-22
integer multiple instructions, D-22
string instructions, D-22
memory control, D-25
memory synchronization, D-22
PowerPC instruction set, 5-18
PowerPC instructions, list
form (format), D-27
function, D-17
legend, D-38
mnemonic, D-1
opcode, D-9
processor control, D-24
segment register manipulation, D-25
system linkage, D-24
TLB management instructions, D-25
trap instructions, D-24
INTA (interrupt request) signal, 2-15
Integer arithmetic instructions, D-17
Integer compare instructions, D-18
Integer load instructions, D-21
Integer logical instructions, D-18
Index-6
INDEX
MPC8240 Integrated Processor User's Manual
Integer multiple instructions, D-22
Integer rotate and shift instructions, D-18–D-19
Integer store instructions, D-21
Integer unit, 5-7
Interface
I O interface
2
IFHPR, 9-15
IFQPR, 9-11
IFTPR, 9-16
IMIMR, 9-14
IMISR, 9-12, 9-12
IPHPR, 9-16
IPTPR, 9-17
MUCR, 9-20
OFHPR, 9-18
OFQPR, 9-12
OFTPR, 9-18
OMIMR, 9-10
OPHPR, 9-19
OPTPR, 9-19
outbound free_list FIFO, 9-8
overview, 9-1
PCI configuration identification, 9-5
QBAR, 9-21
register summary, 9-5
JTAG interface
block diagram, 15-21
registers, 15-22
boundary-scan registers, 15-22
bypass register, 15-22
instruction register, 15-22
status register, 15-22
signal description, 15-21
TAP controller, 15-22
memory interface
configuration registers, 4-23
ECC error, 13-8
errors within a nibble, 13-8
features list, 1-12
Flash write error, 13-7
overview, 1-13
parity, 6-15
physical memory, 13-9
read data parity error, 13-8
refresh overflow error, 13-9
registers, 4-23–4-42
select error, 13-9
signals, see Signals, 2-16
system memory, 13-8
PCI interface
address bus decoding, 7-11
address translation, 7-34
address/data parity error, 13-9
address/data parity errors, 7-19