Motorola MPC8240 User Manual page 158

Processor Interface Configuration Registers
Table 4-26. Bit Settings for PICR1—0xA8 (Continued)
Bits Name
18–17 PROC_TYPE
16 ADDRESS_MAP
15–13 —
addr <a9>
12 FLASH_WR_EN
11 MCP_EN
10 —
9 CF_DPARK
8–7 —
6 ST_GATH_EN
4-30
Reset
Value
10 Processor type. These bits identify the type of processor used in the
system and determine the QREQ, QACK protocol used for power
management.
10 603e
x Address map. This bit controls which address map is used by the
MPC8240. The initial state of this bit is determined by the inverse of the
address map configuration signal (MAA0) during reset.Software that
dynamically changes this bit must ensure that there are no pending PCI
transactions and that there is a sync instruction following the address
map change to allow the update to take effect. See Chapter 3, "Address
Maps," for more information.
0 The MPC8240 is configured for address map B.
1 The MPC8240 is configured for address map A (not supported when
operating in PCI agent mode).
00 Reserved
0 Flash write enable. This bit controls whether the MPC8240 allows write
operations to Flash ROM. Note that if writes to Flash are enabled (with
read-only devices in the banks), and a write transaction occurs, then bus
contention may occur because the write data is driven on the data bus,
and the read-only device starts driving the data bus. This can be avoided
by disabling write capability to the Flash/ROM address space through
the FLASH_WR_EN and/or FLASH_WR_LOCKOUT_EN configuration
bits or by connecting the FOE signal to the output enable of the
read-only device.
0 Flash write is disabled.
1 Flash write is enabled.
0 Machine check enable. This bit controls whether the MPC8240 asserts
MCP (and takes the machine check exception) upon detecting an error.
See Chapter 13, "Error Handling," for more information.
0 Machine check is disabled.
1 Machine check is enabled.
0 Reserved
0 Data bus park. This bit indicates whether the processor core is parked
on the peripheral logic data bus.
0 Processor core is not parked on the data bus.
1 Processor core is parked on the data bus. It is recommended that
software set this bit.
0 Reserved
0 This bit enables store gathering of writes from the processor to PCI
memory space. See Chapter 12, "Central Control Unit," for more
information.
0 Store gathering is disabled.
1 Store gathering is enabled.
MPC8240 Integrated Processor User's Manual
Description