Debug Address Timing - Motorola MPC8240 User Manual

Memory Interface Valid (MIV)
Table 15-6. Example of RAS Encoding For 568-Mbyte Memory System
Partition
Eighth 128-Mbyte partition of
1 Gbyte main memory
Seventh 128-Mbyte partition
of 1 Gbyte main memory
Sixth 128-Mbyte partition of
1 Gbyte main memory
Fifth 128-Mbyte partition of
1Gbyte main memory
Fourth 128-Mbyte partition
of 1 Gbyte main memory
Third 128-Mbyte partition of
1 Gbyte main memory
Second 128-Mbyte partition
of 1 Gbyte main memory
First 128-Mbyte partition of 1
Gbyte main memory

15.3.5 Debug Address Timing

For examples of debug address timing for various memory types, see Figure 15-8 through
Figure 15-16.
15.4 Memory Interface Valid (MIV)
The memory interface valid signal MIV is asserted whenever FPM, EDO, SDRAM, Flash,
or ROM addresses or data are present on the external memory bus. It is intended to help
reduce the number of bus cycles that logic analyzers must store in memory during a debug
trace and is described in Table 15-7. The MIV signal should be sampled with the rising edge
of SDRAM_CLK[0:3].
15-8
Encoded RAS:
Physical
Address [29–27]
0b111 Ending
Starting
0b110 Ending
Starting
0b101 Ending
Starting
Ending
Starting
Ending
0b100
Starting
Ending
Starting
Ending
Starting
Ending
0b011
Starting
Ending
Starting
0b010 Ending
Starting
0b001 Ending
Starting
0b000 Ending
Starting
MPC8240 Integrated Processor User's Manual
Address Bank
0x3FF undefined
0x380
0x37F undefined
0x300
0x2FF undefined
0x280
0x27F undefined
0x238
0x237 7 8 MBytes
0x230
0x22F 6 16 MBytes
0x220
0x21F 5 32 MBytes
0x200
0x1FF 4 64 MBytes
0x1C0
0x1BF 3 64 MBytes
0x180
0x17F 1 128 MBytes
0x100
0x0FF 2 128 MBytes
0x080
0x07F 0 128 MBytes
0x000
Bank Size RAS[0:7]
0xFE
0xFD
0xFB
0xF7
0xEF
0xBF
0xDF
0x7F