Sdram Burst And Single-Beat Transactions - Motorola MPC8240 User Manual

SDRAM Interface Operation
• Mode register set (for configuration)—Allows setting of SDRAM options. These
options are CAS latency, burst type, and burst length.
— CAS latency may be chosen as provided by the preferred SDRAM. (Some
SDRAMs provide CAS latency 1, 2, 3, some provide CAS latency 1, 2, 3, 4).
— Burst type must be set to sequential.
— Although some SDRAMs provide variable burst lengths of 1, 2, 4, 8 page size,
the MPC8240 supports only a burst length of 4 or 8. Burst length 4 must be
selected for operation with a 64 bit memory interface and 8-beat burst lengths are
used with a 32-bit memory interface. Burst lengths of 1 and 2 page size are not
supported by the MPC8240. This command is performed by the MPC8240
during system initialization.
The mode register data (CAS latency, burst length and burst type), is provided by
software at reset in the MPC8240 configuration register and is subsequently
transferred to the SDRAM array by the MPC8240after MEMGO is enabled.
• Self refresh (for long periods of standby)—Used when the device will be in standby
for very long periods of time. Automatically generates internal refresh cycles to keep
the data in both memory banks refreshed. Before execution of this command, all
memory banks must be in a precharged state.
Table 6-10. MPC8240 SDRAM Interface Commands
Command
Bank activate
Precharge
Read
Write
CBR refresh
Mode register set
Self refresh
The MPC8240 automatically issues a precharge command to the SDRAM when the
BSTOPRE or PGMAX intervals have expired, regardless of pending memory transactions
from the PCI bus orprocessorcore. See Section 6.2.7, "SDRAM Page Mode," for more
information about the BSTOPRE and PGMAX parameters. The MPC8240 can perform
precharge cycles concurrent with snoop broadcasts for PCI transactions.

6.2.6 SDRAM Burst and Single-Beat Transactions

In 64-bit data bus mode, the MPC8240 performs a four-beat burst for every transaction
(burst and single-beat); in 32-bit data bus mode, the MPC8240 performs an eight-beat burst
for every transaction (burst and single-beat). The burst is always sequential, and the critical
double word is always supplied first. For example, in 64-bit data bus mode, if the processor
core requests the third double word of a cache block, the MPC8240 reads double words
6-18
SDRAS SDCAS
Asserted Negated
Asserted Negated
Negated Asserted
Negated Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
MPC8240 Integrated Processor User's Manual
WE CS
Negated Asserted Asserted
Asserted Asserted Asserted
Negated Asserted Asserted
Asserted Asserted Asserted
Negated Asserted Asserted
Asserted Asserted Asserted
Negated Asserted Negated
CKE