Inbound Message Interrupt Status Register (Imisr) - Motorola MPC8240 User Manual

Figure 9-9 shows the bits of the IMISR.
0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0
31
Figure 9-9. Inbound Message Interrupt Status Register (IMISR)
Table 9-13 shows the bit settings for the IMISR.
Table 9-13. IMISR Field Descriptions—Offset 0x0_0100
Reset
Bits Name
Value
31–11 — All 0s
8 OFO 0
7 IPO 0
6 — 0
5 IPQI 0
4 DMC 0
R/W
R Reserved
Read Outbound free_list overflow condition
Write 1 0 No overflow condition
1 Indicates that the outbound free_list FIFO head pointer is equal to the
clears
outbound free_list FIFO tail pointer and the queue is full. A machine check is
this bit
signalled to the processor core through the internal mcp signal and a machine
check exception is taken (if enabled). See Chapter 13, "Error Handling." This
bit is set only if the OFOM mask bit in IMIMR is cleared.
Read Inbound post_list overflow condition
Write 1 0 No overflow condition
1 Indicates that the inbound free_list FIFO head pointer is equal to the inbound
clears
free_list FIFO tail pointer and the queue is full. A machine check is signalled to
this bit
the processor core through the internal mcp signal and a machine check
exception is taken (if enabled). This bit is set only if the IPOM mask bit in
IMIMR is cleared.
R Reserved
Read Inbound post queue interrupt (I
Write 1 0 No MFA in the IFQPR
clears 1 Indicates that the PCI master has posted an MFA to the inbound post_list FIFO
through the IFQPR. Interrupt is signalled to the processor core through the
this bit
internal int signal. This bit is set only if the inbound post queue interrupt mask
(IMIMR[IPQIM]) bit is cleared.
R Doorbell register machine check condition
0 No doorbell register machine check condition.This bit is cleared when
IDBR[MC] is cleared.
1 Indicates that a remote processor has generated a machine check condition
(causing assertion of mcp) by setting IDBR[MC]. Note that this bit is set only if
the mask bit, IMIMR[DMCM] = 0.
Chapter 9. Message Unit (with I
IM0I
IM1I
IDI
MCI
IPQI
IPOI
OFOI
9 8 7
Description
O interface)
2
O)
2
I O Interface
2
Reserved
0 0
6 5 4 3 2 1 0
9-13