Address Map B—Processor View In Host Mode - Motorola MPC8240 User Manual

Address Map B
Table 3-1, Table 3-2, Table 3-3, and Table 3-4 show separate views of address map B for
the processor core, a PCI memory device (host mode), a PCI memory device (agent mode),
and a PCI I/O device, respectively. When configured for map B, the MPC8240 translates
addresses across the internal peripheral logic bus and the external PCI bus as shown in
Figure 3-1 through Figure 3-3.
Table 3-1. Address Map B—Processor View in Host Mode
Processor Core Address Range
Hex
0000_0000 3FFF_FFFF
4000_0000 7FFF_FFFF
8000_0000 FDFF_FFFF 2G
FE00_0000 FE7F_FFFF
FE80_0000 FEBF_FFFF 4G - 24M
FEC0_0000 FEDF_FFFF 4G - 20M
FEE0_0000 FEEF_FFFF 4G - 18M
FEF0_0000 FEFF_FFFF
FF00_0000 FF7F_FFFF
FF80_0000 FFFF_FFFF
Table 3-2. Address Map B—PCI Memory Master View in Host Mode
PCI Memory Transaction Address Range
Hex
0000_0000 3FFF_FFFF
4000_0000 7FFF_FFFF
8000_0000 FDFF_FFFF 2G
FE00_0000 FEFF_FFFF 4G - 32M
FF00_0000 FF7F_FFFF
FF80_0000 FFFF_FFFF 4G - 8M
3-2
Decimal
0 1G - 1
1G 2G - 1
4G - 32M - 1
4G - 32M 4G - 32M +
64K - 1
4G - 20M - 1
4G - 18M - 1
4G - 17M - 1
4G - 17M 4G - 16M - 1
4G - 16M 4G - 8M - 1
4G - 8M 4G - 1
Decimal
0 1G - 1
1G 2G - 1
4G - 32M - 1
4G - 16M - 1
4G - 16M 4G - 8M - 1
4G - 1
MPC8240 Integrated Processor User's Manual
PCI Address Range
No PCI cycle
No PCI cycle
8000_0000–FCFF_FFFF
0000_0000–0000_FFFF
0080_0000–00BF_FFFF
CONFIG_ADDR
CONFIG_DATA
Interrupt acknowledge broadcast PCI interrupt acknowledge
If ROM remote, then
FF00_0000–FF7F_FFFF; if
ROM local, then no PCI cycle
If ROM remote, then
FF80_0000–FFFF_FFFF; if
ROM local, then no PCI cycle
Local Memory
Address Range
0000_0000–3FFF_FFFF Local memory space
4000_0000–7FFF_FFFF Reserved
No local memory cycle
No local memory cycle
If ROM local, then
FF00_0000–FF7F_FFF
F; if ROM remote, then
no local memory cycle
If ROM local, then
FF80_0000–FFFF_FFF
F; if ROM remote, then
no local memory cycle
Definition
Local memory space
Reserved
PCI memory space
PCI I/O space (8 Mbytes),
4
0-based
PCI I/O space (4 Mbytes),
5
0-based
PCI configuration address
6
register
PCI configuration data
7
register
32- or 64-bit Flash/ROM
8
space (8 Mbytes)
8-, 32- or 64-bit
Flash/ROM space
9
(8 Mbytes)
Definition
1
2
10, 11
PCI memory space
11
Reserved
32- or 64-bit Flash/ROM space
(8 Mbytes). Read-only area
(writes cause Flash write error).
8-, 32- or 64-bit Flash/ROM
space (8 Mbytes). Read-only
area (writes cause Flash write
9
error).
1
3
8