Motorola MPC8240 User Manual page 178

Memory Control Configuration Registers
Table 4-40. Bit Settings for MCCR3—0xF8 (Continued)
Bits Name
18–15 RAS
6P
14–12 CAS
5
11–9 CP
4
8–6 CAS
3
4-50
Reset
Value
0000 RAS assertion interval for CBR refresh. For DRAM/EDO only. These bits
control the number of clock cycles RAS is held asserted during CBR refresh.
The value for RAS
of the memory interface. See Section 6.3.10, "FPM or EDO DRAM Refresh,"
for more information.
0001 1 clock
0010 2 clocks
0011 3 clocks
... ...
1111 15 clocks
0000 16 clocks
000 CAS assertion interval for page mode access. For DRAM/EDO only. These bits
control the number of clock cycles CAS is held asserted during page mode
accesses. The value for CAS
frequency of the memory interface. Note that when ECC is enabled, CAS
CP must equal four clock cycles. See Section 6.3.5, "FPM or EDO DRAM
4
Interface Timing," for more information.
001 1 clock
010 2 clocks
011 3 clocks
... ...
111 7 clocks
000 8 clocks
000 CAS precharge interval. For DRAM/EDO only. These bits control the number
of clock cycles that CAS must be held negated in page mode (to allow for
column precharge) before the next assertion of CAS. Note that when ECC is
enabled, CAS + CP
5
"FPM or EDO DRAM Interface Timing," for more information.
001 1 clock
010 2 clocks
011 reserved
... ...
111 Reserved
000 Reserved
000 CAS assertion interval for the first access. For DRAM/EDO only. These bits
control the number of clock cycles CAS is held asserted during a single beat or
during the first access in a burst. The value for CAS
DRAMs used and the frequency of the memory interface. See Section 6.3.5,
"FPM or EDO DRAM Interface Timing," for more information.
001 1 clock
010 2 clocks
011 3 clocks
... ...
111 7 clocks
000 8 clocks
MPC8240 Integrated Processor User's Manual
Description
depends on the specific DRAMs used and the frequency
6P
depends on the specific DRAMs used and the
5
must equal four clock cycles. See Section 6.3.5,
4
+
5
depends on the specific
3