Pci Data Parity Error - Motorola MPC8240 User Manual

Error Reporting

13.3.3.2 PCI Data Parity Error

If the MPC8240 is acting as a PCI master and a data parity error occurs, the MPC8240 sets
bit 15 of the PCI status register. This is independent of the settings in the PCI command
register.
If the PCI command register of the MPC8240 is programmed to respond to parity errors
(bit 6 of the PCI command register is set) and a data parity error is detected or signaled
during a PCI bus transaction, the MPC8240 sets the appropriate bits in the PCI status
register (bit 15 is set, and possibly bit 8 is set, as described in the following paragraphs).
If a data parity error is detected by the MPC8240 acting as the master (for example, during
a processor-read-from-PCI transaction) and bit 6 of the PCI command register is set, the
MPC8240 reports the error to the PCI target by asserting PERR and setting bit 8 of the
status register; and tries to complete the transaction, if possible. Also, if PICR1[MCP_EN]
is set, the MPC8240 asserts mcp to report the error to the processor core. These actions also
occur if the MPC8240 is the master and detects the assertion of PERR by the target (for a
write).
If the MPC8240 is acting as a PCI target when the data parity error occurs (on a write), the
MPC8240 asserts PERR and sets ErrDR1[6] (PCI target PERR). If the data has been
transferred, the MPC8240 completes the operation but discards the data. Also, if
PICR1[MCP_EN] is set, the MPC8240 asserts mcp to report the error to the processor core.
If the master asserts PERR during a memory read, the address of the transfer is logged in
the error address register and mcp is asserted (if enabled).
13.3.3.3 PCI Master-Abort Transaction Termination
If the MPC8240, acting as a master, initiates a PCI bus transaction (excluding special-cycle
transactions), but there is no response from any PCI agent (DEVSEL has not been asserted
within five PCI bus clocks from the start of the address phase), the MPC8240 terminates
the transaction with a master-abort and sets the master-abort flag (bit 13) in the PCI status
register. Special-cycle transactions are normally terminated with a master-abort, but these
terminations do not set the master-abort flag in the PCI status register.
If ErrEnR1[1] is set and the MPC8240 terminates a transaction with a master-abort, the
MPC8240 reports the error to the processor core by asserting mcp (provided
PICR1[MCP_EN] is set).
13.3.3.4 Received PCI Target-Abort Error
If a PCI transaction initiated by the MPC8240 is terminated by target-abort, the received
target-abort flag (bit 12) of the PCI status register is set. If ErrEnR2[1] and
PICR1[MCP_EN] are both set and the MPC8240 receives a target-abort, the MPC8240
reports the error to the processor core by asserting mcp (provided PICR1[MCP_EN] is set).
Note that any data transferred in a target-abort transaction may be corrupt.
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