msb
Row x Col
0–4
5 6 7 8 9
13x11 RAS
1
2
CAS
1
0
12x12 RAS
CAS
1
1
1
0
12x11 RAS
CAS
1
0
12x10 RAS
CAS
12x9
RAS
CAS
12x8
RAS
CAS
11x11 RAS
CAS
11x10 RAS
CAS
11x9
RAS
CAS
11x8
RAS
CAS
10x10 RAS
CAS
10x9
RAS
CAS
10x8
RAS
CAS
9x9
RAS
CAS
Figure 6-33. DRAM Address Multiplexing SDMA[12:0]—64 Bit Mode
Physical Address
1
1
1
1
1
0
1
2
3
4
1
1
9 8 7 6 5 4 3 2 1 0
1
0
9 8
1
1
9 8 7 6 5 4 3 2 1 0
1
0
9 8
1
1
9 8 7 6 5 4 3 2 1 0
1
0
9 8
1
1
9 8 7 6 5 4 3 2 1 0
1
0
9 8
1
1
9 8 7 6 5 4 3 2 1 0
1
0
8
1
1
9 8 7 6 5 4 3 2 1 0
1
0
1
9 8 7 6 5 4 3 2 1 0
0
1
9 8
0
1
9 8 7 6 5 4 3 2 1 0
0
9 8
1
9 8 7 6 5 4 3 2 1 0
0
8
1
9 8 7 6 5 4 3 2 1 0
0
9 8 7 6 5 4 3 2 1 0
9 8
9 8 7 6 5 4 3 2 1 0
8
9 8 7 6 5 4 3 2 1 0
8 7 6 5 4 3 2 1 0
8
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
1
1
1
1
1
2
2
2
5
6
7
8
9
0
1
2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
lsb
2
2
2
2
2
2
2
3
3
4
5
6
7
8
9
0
6-53
3
1