Initiator Ready (Irdy)—Input - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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2.2.1.8.2 Initiator Ready (IRDY)—Input
Following is the state meaning for IRDY as an input signal.
State Meaning
2.2.1.9 Lock (LOCK)—Input
The lock (LOCK) signal is an input on the MPC8240. See Section 7.5, "Exclusive Access,"
for more information. Following is the state meaning for the LOCK input signal.
State Meaning
2.2.1.10 Target Ready (TRDY)
The target ready (TRDY) signal is both an input and output signal on the MPC8240.
2.2.1.10.1 Target Ready (TRDY)—Output
Following is the state meaning for TRDY as an output signal.
State Meaning
cycle when it cannot provide valid data to the target. During a read,
the MPC8240 negates IRDY to insert a wait cycle when it cannot
accept data from the target.
Asserted—Indicates another PCI master is able to complete the
current data phase of a transaction.
Negated—If FRAME is asserted, it indicates a wait cycle from
another master. This is used by the MPC8240 to insert wait cycles
when it is a target of a PCI transaction. If FRAME is negated, it
indicates the PCI bus is idle.
Asserted—Indicates that a master is requesting exclusive access to
memory, which may require multiple transactions to complete.
Negated—Indicates that a normal operation is occurring on the bus,
or an access to a locked target is occurring.
Asserted—Indicates that the MPC8240, acting as a PCI target, can
complete the current data phase of a PCI transaction. During a read,
the MPC8240 asserts TRDY to indicate that valid data is present on
AD[31:0]. During a write, the MPC8240 asserts TRDY to indicate
that it is prepared to accept data.
Negated—Indicates that the PCI initiator needs to wait before the
MPC8240, acting as a PCI target, can complete the current data
phase. During a read, the MPC8240 negates TRDY to insert a wait
cycle when it cannot provide valid data to the initiator. During a
write, the MPC8240 negates TRDY to insert a wait cycle when it
cannot accept data from the initiator.
Chapter 2. Signal Descriptions and Clocking
Detailed Signal Descriptions
2-13

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