Bit Rom/Flash Interface—Single-Byte Read Timing - Motorola MPC8240 User Manual

ROM/Flash Interface Operation
The following figures illustrate the 8-bit ROM/Flash interface timing for various read
accesses. Figure 6-58 shows a single-byte read access. Figure 6-59 shows a two-byte
(half-word) read access. Word and double-word accesses require using the cache-line read
access timing shown in Figure 6-60.
Single-byte reads
MCLK
A[0:19]
RCSn
FOE
DATA
2 cycles
(constant)
Data sampled
Figure 6-58. 8-Bit ROM/Flash Interface—Single-Byte Read Timing
Two-byte reads
MCLK
A[0:19]
RCSn
FOE
DATA
2 cycles
(constant)
Data sampled
Figure 6-59. 8-Bit ROM/Flash Interface—Two-Byte Read Timing
6-82
D0
5 cycles
ROMFAL
(minimum)
DATA
ROMFAL 2 cycles
(constant)
MPC8240 Integrated Processor User's Manual
2 cycles ROMFAL
(constant)
DATA
ROMFAL
D1