Parity Error (Perr) - Motorola MPC8240 User Manual

Error Reporting
an external PCI agent asserts SERR two clock cycles after the address phase, the error is
recorded in bit 7 of ErrDR1 and a machine check is generated to the processor core.

13.2.3.2 Parity Error (PERR)

The PERR signal is used to report PCI data parity errors during all PCI transactions except
for PCI special-cycle command transactions. The agent responsible for driving AD[31–0]
on a given PCI bus phase is responsible for driving even parity one PCI clock cycle later on
the PAR signal. That is, the number of 1s on AD[31–0], C/BE[3–0], and PAR equals an
even number.
Two PCI clock cycles after the data phase for which a data parity error is detected, the
PERR signal must be asserted by the agent receiving the data. Only the master may report
a read data parity error; and only the selected target may report a write data parity error.
Bit 6 of the PCI command register decides whether the MPC8240 ignores PERR. Bit 15
and bit 8 of the PCI status register are used to report when the MPC8240 has detected or
reported a data parity error.
13.2.3.3 Nonmaskable Interrupt (NMI)
The NMI signal is, effectively, a PCI sideband signal between the PCI-to-ISA bridge and
the MPC8240. The NMI signal is usually driven by the PCI-to-ISA bridge to report any
nonrecoverable error detected on the ISA bus (normally, through the IOCHCK signal on
the ISA bus). The name nonmaskable interrupt is misleading due to its history in ISA bus
designs. The NMI signal should be connected to GND if it is not used. If PICR1[MCP_EN]
is set, the MPC8240 reports the NMI error to the processor core by asserting mcp.
13.3 Error Reporting
Error detection on the MPC8240 is designed to log the occurrence of an error and also log
information related to the error condition. The individual error detection bits are contained
in the PCI status register, error detection register 1 (ErrDR1), error detection register 2
(ErrDR2), and the inbound message interrupt status register (IMISR). These bits indicate
which error has been detected. (The error detection bits are specifically bits 15, 13, and 12
in the PCI status register, bits 7–4 and 2–0 in ErrDR1, bits 5–3 and 0 in ErrDR2, and bits
8, 7, and 4 in the IMISR.)
The intent of error reporting is to log the information pertaining to the first error that occurs
and prevent additional errors from being reported until the first error is acknowledged and
cleared. For additional errors to be reported, all error detection bits must be cleared. When
an error detection bit is set, the MPC8240 does not report additional errors until all of the
error detection bits are cleared. Note that more than one of the error detection bits can be
set if simultaneous errors are detected. Therefore, software must check whether more than
one bit is set before trying to determine information about the error.
Chapter 13. Error Handling 13-5