Dma Transaction Boundaries For Pci–Memory Transfers - Motorola MPC8240 User Manual

Internal Arbitration
4 Kbytes, then the PCI stream terminates when another PCI master is granted mastership
of the PCI bus. The latency timer parameter in the PCI latency timer register (PLTR) is
further described in Section 4.2.6, "Latency Timer—Offset 0x0D."
As described for memory to memory transfers, nonzero values of the DMR[LMDC] also
increase the time delay between subsequent DMA accesses to local memory for memory
to PCI transfers.
12.2.1.3 DMA Transaction Boundaries for PCI–Memory Transfers
The DMA transaction boundaries for DMA writes to local memory from the PCI bus occur
after the transfer of a single cache line for all values of DMR[LMDC]. As described for the
other cases, nonzero values of the DMR[LMDC] increase the time delay between
subsequent DMA accesses to local memory for PCI to local memory transfers.
12.2.1.4 PCI and DMA Reads from Slow Memory/Port X
As described in Section 7.4.3.2, "Target-Initiated Termination," if the MPC8240 can not
read the first data beat of a burst from local memory within 16 PCI clock cycles, the
transaction is considered to have timed out internally and as a target, the MPC8240
terminates the transaction with a retry. In this case, the CCU continues the access to
memory (as a speculative PCI read) in anticipation of the PCI device requesting the same
transaction at a later time. When the PCI device attempts the read again, the transaction is
rearbitrated with DMA transactions within the PCI interface as a new transaction (not
speculative). If the data has been successfully read into the PCMRB from memory, the
CCU provides the data to the PCI bus.
Similarly, the DMA controller attempts to complete a read from local memory in 32 PCI
clock cycles. If the read does not complete within that time, the CCU continues the access
to memory (as a speculative PCI read in Table 12-2) on behalf of the DMA channel, but the
DMA transaction is considered to have timed out within the PCI interface. After allowing
for rearbitration within the PCI interface unit of the MPC8240, the DMA channel attempts
the read again (not considered speculative). If the read has been completed by the
MPC8240, the CCU provides the data to the DMA unit.
12.2.2 Internal Arbitration Priorities
The overall arbitration for the processor/memory data bus employs the priority scheme
shown in Table 12-2. Note that because the DMA channels function as PCI devices with
respect to the processor/memory data bus, the entries for PCI reads and writes in the table
also implicitly include the cases for DMA reads and writes and they are arbitrated as
described in Section 12.2.1, "Arbitration Between PCI and DMA Accesses to Local
Memory."
Chapter 12. Central Control Unit 12-11