Motorola MPC8240 User Manual page 479

Integrated host processor with integrated pci
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Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes
mtmsr
ori
isync
ori
# save off additional registers to be corrupted
stw
mfspr
stw
mfspr
stw
stw
mfcr
stw
xor
#******************************************************************
# set msr pow bit to go into sleep mode
sync
mfmsr r5
addis r3, r0, 0x0004
ori
r3, r3, 0x0000
or
r5, r3, r5
mtmsr r5
isync
addis r20, r0, 0x0000
ori
r20, r20, 0x0002
stay_here:
addic.
r20, r20, -1
bgt cr0, stay_here
# restore corrupted registers
lwz
mtcrf
lwz
lwz
mtspr
lwz
mtspr
lwz
lwz
sync
rfi
#******************************************************************
# to get out of sleep mode, do a Soft Reset
#******************************************************************
.orig 0x00000100
# force big endian mode
stw
#code read and execute in program order (up until the isync).
stw
mfmsr
ori
ori
ori
xori
ori
r0
r0,r0,r0
r0,r0,r0
r20,0x05f4,r0
r21, srr0
r21,0x05f0,r0
r22, srr1
r22,0x05ec,r0
r23,0x05e8,r0
r23
r23,0x05e4,r0
r0,r0,r0
# get MSR
# turn on POW bit
# turn on ME bit 19
r23,0x05e4,r0
0xff,r23
r23,0x05e8,r0
r22,0x05ec,r0
srr1, r22
r21,0x05f0,r0
srr0, r21
r20,0x05f4,r0
r0,0x05fc,r0
r0,0x05f8,r0
r0,0x05fc,r0
r0
r0,r0,r0
r0,r0,0x0001
r0,r0,r0
r0,r0,0x0001
r0,r0,r0
Chapter 14. Power Management
# put srr0 in r21
# put r21 in 0x05f0
# put srr1 in r22
# put r22 in 0x05ec
# subtract 1 from r20 and set cc
# loop if positive
# Reset handler in low memory
# need nop every second inst to make
# force big endian LE bit
# force big endian LE bit
14-13

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