Pci Write Transactions - Motorola MPC8240 User Manual

PCI Bus Transactions
PCI_SYNC_IN
AD[0:31]
C/BE[0:3]
FRAME
IRDY
DEVSEL
TRDY

7.4.2 PCI Write Transactions

This section describes PCI single-beat write transactions, and PCI burst write transactions.
A PCI write transaction starts with the address phase, occurring when an initiator asserts
FRAME. A write transaction is similar to a read transaction except no turnaround cycle is
needed following the address phase because the initiator provides both address and data.
The data phases are the same for both read and write transactions. Although not shown in
the figures, the initiator must drive the C/BE[3:0] signals, even if the initiator is not ready
to provide valid data (IRDY negated).
Figure 7-5 illustrates a PCI single-beat write transaction. Figure 7-6 illustrates a PCI burst
write transaction.
PCI_SYNC_IN
AD[0:31]
C/BE[0:3]
FRAME
IRDY
DEVSEL
TRDY
7-16
ADDR
CMD Byte enables 1
Figure 7-4. PCI Burst Read Transaction
ADDR
CMD
Figure 7-5. PCI Single-Beat Write Transaction
MPC8240 Integrated Processor User's Manual
DATA1 DATA2
Byte enables 2
DATA
Byte enables