Mpc8240 Integrated Processor Functional Block Diagram - Motorola MPC8240 User Manual

MPC8240 Integrated Processor Overview
MPC8240
Additional features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
2
I C
5 IRQs/
16 Serial
Interrupts
Figure 1-1. MPC8240 Integrated Processor Functional Block Diagram
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC
interrupt controller, a message unit (and I
processor core is a full-featured, high-performance processor with floating-point support,
1-2
Processor Core Block
Processor
Branch
PLL
Processing
(BPU)
System
Integer
Register
Unit
Unit
(IU)
(SRU)
Peripheral Logic Block
Address
(32 bit)
Message
Unit
(with I O)
2
Central
Control
Unit
DMA
Controller
2
I C
Controller
PCI Bus
Interface Unit
EPIC
Interrupt
Address
Controller
Translator
/Timers
32-Bit
PCI Interface
MPC8240 Integrated Processor User's Manual
(64 bit) Two-instruction Fetch
Instruction Unit
Unit
(64-bit) Two-instruction Dispatch
Load/Store
Unit
(LSU)
Data
MMU
16-Kbyte
Data
Cache
Peripheral Logic
Bus
Data (64 bit)
Data Path
ECC Controller
Memory
Controller
Configuration
Registers
Peripheral Logic
PLL
PCI
Arbiter
Five
Request/Grant
Pairs
O controller), and an I
2
Floating-
Point
Unit
(FPU)
64 bit
Instruction
MMU
16-Kbyte
Instruction
Cache
Data Bus
(32- or 64-bit)
with 8-bit Parity
or ECC
Address/Control
DRAM/SDRAM/
ROM/Flash/Port X
SDRAM Sync In
SDRAM Sync Out
DLL
SDRAM Clocks
PCI Clock In
Fanout
PCI Bus Clocks
Buffers
OSC In
2
C controller. The