Motorola MPC8240 User Manual page 220

• Data path buffering—72 bits (64-bit data and 8-bit parity)
— Reduces loading on the internal processor core bus
— Reduces loading of the drivers of the memory system
— Reduces signal trace delay known as time-of-flight (TOF)
• Parity—Supports normal parity and read-modify-write (RMW)
• Error checking and correction (ECC)—64-bit only
— DRAM ECC—Located in the central control unit (CCU)
— SDRAM ECC—Located in-line with the data path buffers
The MPC8240 is designed to control a 32- or 64-bit data path to main memory (SDRAM
or DRAM). The MPC8240 can be configured to check parity or ECC on memory reads.
Parity checking and generation can be enabled with 4 parity bits for a 32-bit data path or 8
parity bits for 64-bit data path. Concurrent ECC is only generated for 64-bit data path with
8 syndrome bits.
The MPC8240 supports SDRAM or DRAM bank sizes from 1 to 128 Mbytes and provides
bank start address and end address configuration registers. However the MPC8240 does not
support mixed SDRAM or DRAM configurations.
The MPC8240 can be configured so that appropriate row and column address multiplexing
occurs for each physical bank. Addresses (DRAM or SDRAM) and bank selects (SDRAM
only) are provided through a 14-bit interface for SDRAM and 13-bit interface for DRAM.
ROM/Flash systems are supported by up to 21 address bits, 2 bank selects, 1 write enable
and 1 output enable. Figure 6-1 is a block diagram of the memory interface.
6-2 MPC8240 Integrated Processor User's Manual