Sdram Registered Memory Interface - Motorola MPC8240 User Manual

External Data from SDRAM
Internal Bus Clock
Internal Data to SDRAM
Output Enable
Figure 6-5. SDRAM Registered Memory Interface
The in-line buffer mode interface is shown in Figure 6-6. In-line buffer mode allows for
ECC or parity generation and checking between the internal processor core bus and the
external SDRAM data bus. In-line ECC is described in Section 6.2.10, "SDRAM In-Line
ECC."
External Data from SDRAM
Internal Bus Clock
Error signals to Peripheral Logic
Internal Data to SDRAM
Output enable
Figure 6-6. . SDRAM In-line ECC/Parity Memory Interface
Q D
D Q
ECC or Parity
check/correct
Q D
Parity
Generate
collect
error
signals
Parity Check
D Q
ECC or Parity
Generate
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
Data Signals
SDRAM data path
Q D
Data Signals
SDRAM data path
D Q
6-15