Address Map Interactions - Motorola MPC8240 User Manual

Address Map Interactions

When the source and destination addresses are misaligned, the DMA transfer occurs after
32 bytes of data have been stored in the queue. For the last transfer, data in the queue can
be less than 32 bytes. The DMA controller begins writing data to local memory space
beginning at the destination address. The process is repeated until there is no more data to
transfer or an error condition occurs while accessing memory.
8.5 Address Map Interactions
Because of the flexibility of the MPC8240's DMA controller, certain interactions can occur
related to the specific address map and mode in which MPC8240 is operating. Refer to
Chapter 13, "Error Handling," for information on the reporting of these error conditions.
8.5.1 Attempted Writes to Local ROM/Port X Space
If the MPC8240 is in either host or agent mode, CDAR[CCT] indicates that the transferred
address is for local memory, and the address falls between 0xFF00_0000 and
0xFFFF_FFFF, only read operations are allowed. Attempts to program the DMA controller
to write to this space (comprising the local ROM/Port X space) under these conditions
results in a Flash write error and DSR[LME] is set if ErrDR1[5] is set before the DMA unit
completes transferring the data. (For a DMA transfer with a small byte count, less than a
cache line, it is possible for the DMA posted write to the CCU buffer to complete prior to
the start of the actual write to local memory.) Additionally, this error condition causes the
assertion of the internal mcp signal, and a machine check exception (if enabled).
See Chapter 13, "Error Handling," for more information about the internal mcp signal.
8.5.2 Host Mode Interactions
The following subsections describe cases of interactions with the host mode address maps.
8.5.2.1 PCI Master Abort when PCI Bus Specified for Lower 2-Gbyte
Space
If the MPC8240 is in host mode and a transferred address falls within the lower 2-Gbyte
space (0x0000_0000 to 0x7FFF_FFFF) on the PCI bus (specified by CDAR[CTT]), then
the MPC8240 issues the transaction to the PCI bus with that address. However, this address
space is reserved for the host controller; therefore, no PCI target responds to the transaction,
and the transaction terminates with a PCI master abort and the PE bit in DMR is set.
8.5.2.2 Address Alias to Lower 2-Gbyte Space
If the MPC8240 is in host mode, the CDAR[CTT] indicates that the transferred address is
for local memory and the address falls between 0x8000_0000 and 0xFEFF_FFFF, then the
transaction is issued to local memory and the address is aliased to the lower 2-Gbyte space.
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