Memory Control Configuration Registers - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Memory Control Configuration Registers
Table 4-37. Bit Settings for the AMBOR—0xE0 (Continued)
Bits
Name
3
PCI_COMPATIBILITY_
HOLE
2
PROC_COMPATIBILITY_
HOLE
1–0
4.10 Memory Control Configuration Registers
The four 32-bit memory control configuration registers (MCCRs) set all RAM and ROM
parameters. These registers are programmed by initialization software to adapt the
MPC8240 to the specific memory organization used in the system. After all the memory
configuration parameters have been properly configured, the initialization software turns on
the memory interface using the MEMGO bit in MCCR1.
Note that the RAM_TYPE bit in MCCR1 must be cleared (to select SDRAM mode) before
either the REGISTERED or buffer mode bits in MCCR4 are set to one. In-line or registered
buffer modes are not supported in FPM/EDO DRAM systems and attempts to configure
them may result in data corruption. This restriction includes the time between system reset
and the setting of the MEMGO bit; therefore, it may dictate the order in which the memory
controller configuration registers are written. It is recommended that the user first write
MCCR1, 2, 3, and 4, in order, without setting the MEMGO bit. Afterwards, the user should
perform a read-modify-write operation to set the MEMGO bit in MCCR1.
Figure 4-29 and Table 4-38 show the memory control configuration register 1 (MCCR1)
format and bit settings.
4-42
Reset
Value
0
This bit is used only for address map B (not supported in agent mode).
0 The MPC8240, as a PCI target, responds to PCI addresses in the
range 0x000A_0000–0x000F_FFFF and forwards the transaction to
system memory.
1 The MPC8240, as a PCI target, does not respond to PCI addresses
in the range 0x000A_0000–0x000F_FFFF.
0
This bit is used only for address map B (not supported in agent mode).
0 The MPC8240 forwards processor-initiated transactions in the
address range 0x000A_0000–0x000B_FFFF to system memory.
1 The MPC8240 forwards processor-initiated transactions in the
address range 0x000A_0000–0x000B_FFFF to the PCI memory space.
00
Reserved
MPC8240 Integrated Processor User's Manual
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