I2Csr Field Descriptions—Offset 0X0_300C - Motorola MPC8240 User Manual

2
I C Register Descriptions
Table 10-7 describes the bits settings of the I2CSR.
Table 10-7. I2CSR Field Descriptions—Offset 0x0_300C
Reset
Bits Name
Value
31–8 — 0
7 MCF 1
6 MAAS 0
5 MBB 0
4 MAL 0
3 — 0
2 SRW 0
1 MIF 0
0 RXAK 1
10-12
R/W
R Reserved
R Data transferring. While one byte of data is being transferred, this bit is cleared. It
is set by the falling edge of the 9th clock of a byte transfer.
0 Transfer in progress. MCF is cleared when I2CDR is read in receive mode or
when I2CDR is written in transmit mode.
1 Transfer complete
R Addressed as a slave. When the value in I2CADR matches the calling address,
this bit is set. The processor is interrupted (by the int signal through EPIC),
provided I2CCR[MIEN] is set. Next, the processor must check the SRW bit and set
I2CCR[MTX] accordingly. Writing to the I2CCR automatically clears this bit.
0 Not addressed as a slave
1 Addressed as a slave
R Bus busy. This bit indicates the status of the bus. When a START condition is
detected, MBB is set. If a STOP condition is detected, it is cleared.
2
0 I C bus is idle.
2
1 I C bus is busy.
R/W Arbitration lost. This bit is automatically set when the arbitration procedure is lost.
Note that the MPC8240 does not automatically retry a failed transfer attempt.
0 Arbitration is not lost. Can only be cleared by software.
1 Arbitration is lost. See Section 10.2.6, "Arbitration Procedure."
R Reserved
R Slave read/write. When MAAS is set, SRW indicates the value of the R/W
command bit of the calling address sent from the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
This bit is valid only when both of the following occur:
• A complete transfer has occurred and no other transfers have been initiated,
2
• The I C interface is configured as a slave and has an address match.
By checking this bit, the processor can select slave transmit/receive mode
according to the command of the master.
R/W Module interrupt. The MIF bit is set when an interrupt is pending, causing a
processor interrupt request (provided I2CCR[MIEN] is set).
0 No interrupt pending. Can only be cleared by software
1 Interrupt pending. MIF is set when one of the following events occurs:
• One byte of data is transferred (set at the falling edge of the 9th clock)
• The value in I2CADR matches the calling address in slave-receive mode
• Arbitration is lost. See Section 10.2.6, "Arbitration Procedure."
R Received acknowledge. The value of SDA during the acknowledge bit of a bus
cycle. If the received acknowledge bit (RXAK) is low, it indicates that an
acknowledge signal has been received after the completion of eight bits of data
transmission on the bus. If RXAK is high, it means no acknowledge signal has
been detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
MPC8240 Integrated Processor User's Manual
Description