Motorola MPC8240 User Manual page 625

Numerics
603e core, see Processor core
A
Abbreviations, xlvi
Acronyms, xlvi
Address maps
address translation, 3-11
addressing on PCI bus, 7-11
debug address maps, 15-6
DMA controller interactions, 8-10
agent mode, 8-11
host mode, 8-10
emulation mode address map, 4-41
EPIC unit, 11-4
ESCR1 register, 4-41
EUMB (embedded utilities memory block), 3-18
registers
peripheral control and status
registers, 3-18, 3-19
runtime registers, 3-18
examples, configuration sequences, 4-3
map A
direct-access PCI configuration, A-6
overview, 3-1
PCI I/O master view, A-2
map B
overview, 3-1
PCI I/O master view, 3-3
PCI memory master view in agent mode, 3-3
processor view in host mode, 3-2, 3-8
overview, 3-1
Addressing
address translation, 3-11
address translation registers, 3-14
EUMB (embedded utilities memory block), 3-18
inbound PCI address translation, 3-11
outbound PCI address translation, 3-13
PCI bus
addressing, 7-13
configuration space, 7-13
I/O space, 7-12
memory space, 7-12
Addressing modes, 5-18
ADn (PCI address/data bus) signals, 2-9, 7-12
Agent mode
PCI address translation, 7-34
INDEX
Alignment
byte alignment, 7-13, B-2
Arbitration
2
I C arbitration procedure, 10-5
arbitration loss, 10-6
internal arbitration
in-order execution, 12-9
out-of-order execution, 12-1
PCI bus arbitration, 7-4
ARn (ROM address) signals, 2-21
AS (address strobe) signal, 2-23, 4-46, 6-90
B
BAT registers, see Block address translation
BCR (byte count) register, 8-21
Big-endian mode
accessing configuration registers, 4-3
byte lane translation, B-2
byte ordering, B-2
DMA descriptors, 8-14
LE_MODE bit, 4-31
PCI memory space, B-3, B-5
BIST (built-in self test) control register, 4-10
Block address translation
BAT registers
BAT area lengths
WIMG bits, E-16
Block diagrams
clock subsystem block diagram, 2-34
DMA controller, 8-2
EDO DRAM interface, 6-46
EPIC controller, 11-3
EPIC unit internal block diagram, 11-9
FPM interface, 6-46
memory interface, 6-3
MPC8240 functional block diagram, 1-2
MPC8240 integrated processor core, 1-9
peripheral logic block diagram, 1-11
Port X interface, 6-90
processor core, 5-2
ROM interface, 6-73
SDRAM interface, 6-6
BO operand encodings, E-9
Boundary-scan registers, 15-22
Branch instructions
BO operand encodings, E-9
branch instructions, D-24
Index Index-1