Fpm Or Edo Dram Interface Timing - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
Table 6-21. Memory Interface Configuration Register Fields (Continued)
Register Field
ECC_EN
BUF_TYPE[1]
BUF_TYPE[0]
WRITE_PARITY_CHK
After configuration of all these parameters is complete, the system software must set the
configuration bit MEMGO which enables the memory controller. The MPC8240 performs
one CAS before RAS (CBR) refresh cycle each time REFINT elapses. After eight
refreshes, the main memory array is available for read and write accesses.

6.3.5 FPM or EDO DRAM Interface Timing

The read and write timing for DRAM is also controlled through programmable registers.
These registers are programmed by system software at system start-up to control:
• RAS precharge time (RP
• RAS to CAS delay time (RCD
• CAS pulse width for the first access (CAS
• CAS precharge time (CP
• CAS pulse width in page mode (CAS
All signal transitions occur on system clock rising edges. Figure 6-36 shows DRAM read
timing with the programmable variables. Figure 6-38 shows DRAM write timing with the
programmable variables. As shown, the provided timing variables are applicable to both
read and write timing configuration. System software is responsible for optimal
configuration of these parameters after reset. This configuration process must be completed
at system start-up before any attempts to access DRAM. The actual values used by boot
code depend on the memory technology used.
Note that no more than 8 PCI clock cycles should elapse between successive assertions of
CAS within a burst.
Table 6-22 defines the timing parameters for FPM or EDO DRAM. Subscripts identify
timing variables.
6-56
ECC enable
Registered data path = 0 (off)
Cleared. In-line data path disabled.
Enable write path parity error reporting
)
1
)
2
)
4
5
MPC8240 Integrated Processor User's Manual
Description
)
3
)
Configuration
Register (and offset)
MCCR2 @ <F4>
MCCR4 @ <FC>
MCCR4 @ <FC>
MCCR2 @ <F4>