Next Descriptor Address Registers (Ndars) - Motorola MPC8240 User Manual

8.7.8 Next Descriptor Address Registers (NDARs)

The NDARs contain the address for the next descriptor in memory. Software is not expected
to initialize this register. This register contains valid information only after the DMA engine
has fetched a descriptor that was pointed to by the CDAR. All data bits, with the exception
of EOTD, belong to the next descriptor to be loaded and executed. When the data bits are
transferred to the CDAR, the bits become effective for the current transfer.
Figure 8-10 shows the bits in the NDARs.
31
Figure 8-10. Next Descriptor Address Register (NDAR)
Table 8-4 describes the bit settings for the NDARs.
Table 8-9. NDAR Field Descriptions—Offsets 0x124, 0x224
Reset
Bits Name
Value
31–5 NDA All 0s
4 NDSNEN 0
3 NDEOSIE 0
2–1 NDCTT 00
0 EOTD 0
NDA
R/W
RW Next descriptor address. Contains the next descriptor address of the buffer
descriptor in memory; must be aligned on an 8-word boundary.
RW Next descriptor snoop enable. This bit is valid for both chaining and direct
modes.
0 Disables snooping
1 Enables processor core snooping for DMA transactions.
RW Next descriptor end-of-segment interrupt enable. Interrupt mechanism used
depends on the setting of DMR[IRQS]. This bit is valid only for chaining mode.
0 End-of-segment interrupt disabled
1 Generates an interrupt if the DMA transfer for the next descriptor is finished.
RW Next descriptor channel transfer type. These two bits specify the type/direction
of the DMA transfer. These bits are valid for both chaining and direct modes.
00 Local memory to local memory transfer
01 Local memory to PCI transfer
10 PCI to local memory transfer
11 PCI to PCI transfer
RW End-of-transfer descriptor. This bit is ignored in direct mode.
0 This descriptor is not the last descriptor in memory.
1 Indicates that this descriptor is the last descriptor in memory. If this bit is set,
NDAR bits 4, 3, 2, and 1 are ignored and the DMA controller finishes after the
current buffer transaction is finished.
Chapter 8. DMA Controller
DMA Register Descriptions
EOTD
NDCTT
NDEOSIE
NDSNEN
5
Description
4 3 2 1 0
8-23