Table of Contents
Advertisement
I
O Interface
2
Table 9-13. IMISR Field Descriptions—Offset 0x0_0100 (Continued)
Reset
Bits
Name
Value
3
IDI
0
2
—
0
1
IM1I
0
0
IM0I
0
9.3.4.2.2 Inbound Message Interrupt Mask Register (IMIMR)
The IMIMR contains the interrupt mask of the I
events generated by a remote PCI master. Figure 9-10 shows the bits of the IMIMR.
0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0
31
Figure 9-10. Inbound Message Interrupt Mask Register (IMIMR)
9-14
R/W
R
Inbound doorbell interrupt
0 No inbound doorbell interrupt. This bit is cleared when the processor core
clears IDBR[30–0].
1 Indicates that at least one of IDBR[30–0] is set. Interrupt is signalled to the
processor core through the internal int signal. This bit is set only if the mask bit
(IDIM) in IMIMR is cleared.
R
Reserved
Read;
Inbound message 1 interrupt
write 1
0 No inbound message 1 interrupt.
1 Indicates an inbound message 1 interrupt condition (a write occurred to IMR1
clears
from a remote PCI master). Interrupt is signalled to the processor core through
this bit
the internal int signal. This bit is set only if the mask bit (IM1IM) in IMIMR is
cleared.
Read;
Inbound message 0 interrupt
write 1
0 No inbound message 0 interrupt
1 Indicates an inbound message 0 interrupt condition (a write occurred to IMR0
clears
from a remote PCI master). Interrupt is signalled to the processor core through
this bit
the internal int signal. This bit is set only if the mask bit (IM0IM) in IMIMR is
cleared.
MPC8240 Integrated Processor User's Manual
Description
O, doorbell register, and message register
2
IM0IM
IM1IM
IDIM
MCIM
IPQIM
IPOIM
OFOIM
9
8
Reserved
0
0
7
6
5
4
3
2
1
0
Advertisement
Chapters
Table of Contents
