Pci Bus Arbitration - Motorola MPC8240 User Manual

PCI Bus Arbitration

7.2 PCI Bus Arbitration
PCI bus arbitration is access-based. Bus masters must arbitrate for each access performed
on the bus. The PCI bus uses a central arbitration scheme where each master has its own
unique request (REQ) output and grant (GNT) input signal. A simple request-grant
handshake is used to gain access to the bus. Arbitration for the bus occurs during the
previous access so that no PCI bus cycles are consumed due to arbitration (except when the
bus is idle).
The MPC8240 provides bus arbitration logic for the MPC8240 and up to five other PCI bus
masters. The on-chip PCI arbiter is independent of host or agent mode. The on-chip PCI
arbiter functions in both host and agent modes, or it can be disabled to allow for an external
PCI arbiter.
A configuration signal (MAA2) sampled at the negation of the reset signal (HRST_CTRL)
determines if the on-chip PCI arbiter is enabled (low) or disabled (high). The on-chip PCI
arbiter can also be enabled or disabled by programming bit 15 of the PCI arbitration control
register (PACR). Note that the sense of bit 15 corresponds to the inverse of the polarity of
the configuration signal (that is, when bit 15 = 1 the arbiter is enabled, and when bit 15 = 0
the arbiter is disabled). See Section 2.4, "Configuration Signals Sampled at Reset," for
more information on the reset configuration signals.
If the on-chip PCI arbiter is enabled, a request-grant pair of signals is provided for each
external master (REQ[0:4] and GNT[0:4]). In addition, there is an internal request/grant
pair for the internal master state machine of the MPC8240 that governs processor accesses
to PCI and PCI transactions initiated by the DMA controller (which functions as a PCI
agent). If the on-chip PCI arbiter is disabled, the MPC8240 uses the GNT0 signal as an
output to issue its request to the external arbiter and uses the REQ0 signal as an input to
receive its grant from the external arbiter.
7.2.1 Internal Arbitration for PCI Bus Access
The internal state machine that arbitrates between the two on-chip DMA channels and
processor accesses to the PCI bus is separate from the on-chip PCI bus arbiter that controls
the arbitration between the MPC8240 and external PCI bus masters (enabled by the PCI
arbiter control register at offset 0x46). This internal arbiter for MPC8240 resources is
always enabled, and its output is the combined internal request/grant pair for the MPC8240.
The order of progression of priorities between these accesses is shown in Figure 7-1.
7-4 MPC8240 Integrated Processor User's Manual