Example Rom Debug Address, Miv, And Maa Timings For Burst Read - Motorola MPC8240 User Manual

Memory Interface Valid (MIV)
SDRAM_
CLK[0:3]
CS
A[1:0]
ROMFAL ROMNAL ROMNAL ROMNAL
A[19:2]
DATA
DATA0 DATA1 DATA2 DATA3
DEBUG
VALID VALID VALID VALID
ADDRESS
MIV
MAA
VALID
NOTES
:
1. ROMFAL (ROM First Access Latency) = 0–15 clocks.
2. ROMNAL (ROM Nibble Access Latency) = 0–9 clocks.
3. Memory configuration BURST = 1.
Figure 15-14. Example ROM Debug Address, MIV, and MAA Timings For Burst Read
Chapter 15. Debug Features 15-15