Motorola MPC8240 User Manual page 32

Table
Number
4-17 Output Driver Control Register Bit Definitions-0x73.............................................. 4-20
4-18 CLK Driver Control Register Bit Definitions-0x74................................................. 4-22
4-19 Embedded Utilities Memory Base Address Register-0x78...................................... 4-23
4-20 Bit Settings for Memory Starting Address Registers 1 and 2..................................... 4-24
4-21 Bit Settings for Extended Memory Starting Address Registers 1 and 2..................... 4-25
4-22 Bit Settings for Memory Ending Address Registers 1 and 2 ...................................... 4-25
4-23 Bit Settings for Extended Memory Ending Address Registers 1 and 2...................... 4-26
4-24 Bit Settings for Memory Bank Enable Register-0xA0............................................. 4-27
4-25 Bit Settings for Memory Page Mode Register-0xA3 ............................................... 4-28
4-26 Bit Settings for PICR1-0xA8 ................................................................................... 4-29
4-27 Bit Settings for PICR2-0xAC................................................................................... 4-32
4-28 Bit Settings for ECC Single-Bit Error Counter Register-0xB8................................ 4-33
4-29 Bit Settings for ECC Single-Bit Error Trigger Register-0xB9 ................................ 4-34
4-30 Bit Settings for Error Enabling Register 1 (ErrEnR1)-0xC0 ................................... 4-35
4-31 Bit Settings for Error Detection Register 1 (ErrDR1)-0xC1.................................... 4-36
4-32 Bit Settings for Internal Processor Bus Error Status Register-0xC3........................ 4-37
4-33 Bit Settings for Error Enabling Register 2 (ErrEnR2)-0xC4 ................................... 4-38
4-34 Bit Settings for Error Detection Register 2 (ErrDR2)-0xC5.................................... 4-39
4-35 Bit Settings for PCI Bus Error Status Register-0xC7 .............................................. 4-40
4-36 Bit Settings for Processor/PCI Error Address Register-0xC8.................................. 4-40
4-37 Bit Settings for the AMBOR-0xE0 .......................................................................... 4-41
4-38 Bit Settings for MCCR1-0xF0 ................................................................................. 4-43
4-39 Bit Settings for MCCR2-0xF4 ................................................................................. 4-46
4-40 Bit Settings for MCCR3-0xF8 ................................................................................. 4-49
4-41 Bit Settings for MCCR4-0xFC................................................................................. 4-52
5-1 HID0 Field Descriptions ............................................................................................. 5-13
5-2 HID0[BCLK] and HID0[ECLK] CKO Signal Configuration .................................... 5-16
5-3 HID1 Field Descriptions ............................................................................................. 5-17
5-4 HID2 Field Descriptions ............................................................................................. 5-17
5-5 CCU Responses to Processor Transactions ................................................................ 5-24
5-6 Transactions Reflected to the Processor for Snooping ............................................... 5-25
5-7 Exception Classifications for the Processor Core....................................................... 5-28
5-8 Exceptions and Conditions ......................................................................................... 5-28
5-9 Integer Divide Latency ............................................................................................... 5-33
5-10 Major Differences between MPC8240's Core and the MPC603e User's Manual ..... 5-34
6-1 Memory Interface Signal Summary.............................................................................. 6-3
6-2 Memory Address Signal Mappings .............................................................................. 6-5
6-3 SDRAM Data Bus Lane Assignments.......................................................................... 6-7
6-4 Unsupported Multiplexed Row and Column Address Bits........................................... 6-9
6-5 Supported SDRAM Device Configurations................................................................ 6-10
6-6 SDRAM Address Multiplexing SDBA[1:0] and SDMA[12:0]-32-Bit Mode ......... 6-11
6-7 SDRAM Address Multiplexing SDBA[1:0]and SDMA[12:0]-64-Bit Mode .......... 6-12
6-8 Memory Data Path Parameters ................................................................................... 6-13
xxxii
TABLES
Title
MPC8240 Integrated Processor User's Manual
Page
Number