B-8 Four-Byte Transfer To Pci Memory Space—Little-Endian Mode - Motorola MPC8240 User Manual

0
xx
AD[3–0]
Figure B-8. Four-Byte Transfer to PCI Memory Space—Little-Endian Mode
Core
Processor
A[28–31] 0 0 0 0
Munge address
XOR with 100
PA[28–31]
0 1 0 0
1 2 3 4 5
xx xx xx D4 D5
CDU
Unmunges address
Swaps byte lanes
Runs PCI memory transaction
During address phase
0 0 0 0
(AD[1–0] = 0b00 for memory space access)
3 2 1
D4 D5 D6 D7
D4 D5
PCI Memory Space
Appendix B. Bit and Byte Ordering
Byte lanes
6 7
Internal peripheral logic data bus
D6 D7
PCI byte lanes (C/BE[3–0] asserted)
0
PCI data bus (AD[31–0] during data phase)
D6 D7 0x00
0x08
Little-Endian Mode
B-11