D.2 Instructions Sorted By Opcode - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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D.2 Instructions Sorted by Opcode

Table D-2 lists the instructions defined in the PowerPC architecture in numeric order by
opcode.
Key:
Reserved bits
Table D-2. Complete Instruction List Sorted by Opcode
Name
0
4
tdi
0 0 0 0 1 0
twi
0 0 0 0 1 1
mulli
0 0 0 1 1 1
subfic
0 0 1 0 0 0
cmpli
0 0 1 0 1 0
cmpi
0 0 1 0 1 1
addic
0 0 1 1 0 0
addic.
0 0 1 1 0 1
addi
0 0 1 1 1 0
addis
0 0 1 1 1 1
bcx
0 1 0 0 0 0
sc
0 1 0 0 0 1
bx
0 1 0 0 1 0
mcrf
0 1 0 0 1 1
bclrx
0 1 0 0 1 1
crnor
0 1 0 0 1 1
rfi
0 1 0 0 1 1
crandc
0 1 0 0 1 1
isync
0 1 0 0 1 1
crxor
0 1 0 0 1 1
crnand
0 1 0 0 1 1
crand
0 1 0 0 1 1
creqv
0 1 0 0 1 1
crorc
0 1 0 0 1 1
cror
0 1 0 0 1 1
bcctrx
0 1 0 0 1 1
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TO
A
TO
A
D
A
D
A
crfD
0 L
A
crfD
0 L
A
D
A
D
A
D
A
D
A
BO
BI
0 0 0 0 0
0 0 0 0 0
crfD
0 0
crfS
BO
BI
crbD
crbA
0 0 0 0 0
0 0 0 0 0
crbD
crbA
0 0 0 0 0
0 0 0 0 0
crbD
crbA
crbD
crbA
crbD
crbA
crbD
crbA
crbD
crbA
crbD
crbA
BO
BI
Appendix D. PowerPC Instruction Set Listings
Instructions Sorted by Opcode
Instruction not implemented in the MPC8240
BD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LI
0 0
0 0 0 0 0
0 0 0 0 0
crbB
0 0 0 0 0
crbB
0 0 0 0 0
crbB
crbB
crbB
crbB
crbB
crbB
0 0 0 0 0
SIMM
SIMM
SIMM
SIMM
UIMM
SIMM
SIMM
SIMM
SIMM
SIMM
AA LK
1 0
AA LK
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0
LK
0 0 0 0 1 0 0 0 0 1
0 0 0 0 1 1 0 0 1 0
0 0 1 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 1
0 0 1 1 1 0 0 0 0 1
0 1 0 0 0 0 0 0 0 1
0 1 0 0 1 0 0 0 0 1
0 1 1 0 1 0 0 0 0 1
0 1 1 1 0 0 0 0 0 1
1 0 0 0 0 1 0 0 0 0
LK
D-9
0
0
0
0
0
0
0
0
0
0
0

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