Pci Bus Error Status Register—0Xc7 - Motorola MPC8240 User Manual

Error Handling Registers
Figure 4-26 shows the PCI bus error status register.
Figure 4-26. PCI Bus Error Status Register—0xC7
Table 4-35 describes the bits of the PCI bus error status register.
Table 4-35. Bit Settings for PCI Bus Error Status Register—0xC7
Bits Name
7–5 —
4 MPC8240
master/target status
3–0 C/BE[3:0]
The processor/PCI error address register maintains address bits for either the processor bus
or the PCI bus transaction that generated an error as shown in Figure 4-27.
31
Figure 4-27. Processor/PCI Error Address Register—0xC8
Table 4-36 describes the bits of processor/PCI error address register.
Table 4-36. Bit Settings for Processor/PCI Error Address Register—0xC8
Bits Name
Error address
31–24
23–16
15–8
7–0
4-40
MPC8240
Master/Target Status
0 0 0
7
Reset
Value
000 Reserved
0 MPC8240 master/target status
0 MPC8240 is the PCI master.
1 MPC8240 is the PCI target.
0000 These bits maintain a copy of C/BE[3:0]. When a PCI bus error is
detected, these bits are latched until all error flags are cleared.
Reset
Value
0x00 A[24:31] or AD[7:0]—Dependent on whether the error is a processor bus error or
a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
0x00 A[16:23] or AD[15:8]—(Dependent on whether the error is a processor bus error
or a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
0x00 A[8:15] or AD[23:16]—Dependent on whether the error is a processor bus error
or a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
0x00 A[0:7] or AD[31:24]—Dependent on whether the error is a processor bus error or
a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
MPC8240 Integrated Processor User's Manual
C/BE[3:0]
5 4 3 0
Description
Error Address
Description
Reserved
0