Motorola MPC8240 User Manual page 637

PVR, E-12, E-15
RPA, E-22
SRR0/SRR1, E-19
SRs, E-18
TB, E-13
TBL/TBU, E-10
user-level
FPR0–FPR31, E-4
FPSCR, E-6
GPR0–GPR31, E-4
LR, E-9
TBL/TBU, E-19
XER, E-8
VEA register set, E-10
REQ (PCI bus request) signal, 2-8, 7-4
Reservation set, lwarx/stwcx., 5-24
ROM interface
address multiplexing, 6-77
block diagram, 6-73
operation, 6-73
overview, 6-73
timing, 6-78
write operations, 6-83
write timing, 6-84
Rotate and shift instructions, D-18–D-19
RPA (required physical address), E-23
Runtime registers, see EUMB registers, 3-18
S
S_CLK (serial interrupt clock) signal, 2-24
S_FRAME (serial interrupt frame) signal, 2-24
S_INT (serial interrupt stream) signal, 2-24
S_RST (serial interrupt reset) signal, 2-24
SAR (source address) register, 8-20
SCL (serial clock) signal, 2-25
SDA (serial data) signal, 2-25
SDCAS (SDRAM column address strobe) signal, 2-22
SDRAM interface
address multiplexing, 6-10
block diagram, 6-6
data interface, 6-13
ECC, 6-27
JEDEC functionality, 6-17
mode-set command timing, 6-26
operation, 6-6
organizations supported, 6-9
overview, 6-6
page mode retention, 6-19
parity, 6-26
power saving modes, 6-33
power-on initialization, 6-16
programmable parameters, 6-16
registered DIMM mode, 6-29
RMW parity, 6-26
INDEX
system configuration, 6-14
SDRAM_CLK (SDRAM clock outputs) signals, 2-33
SDRAM_SYNC_IN (SDRAM feedback clock)
signal, 2-33
SDRAM_SYNC_OUT (SDRAM clock synchronize
out), 2-33
SDRAS (SDRAM row address strobe) signal, 2-21
Segment registers
SR manipulation instructions, D-25
T bit, 2
T-bit, E-18
SERR (system error) signal, 2-14, 7-32, 13-4
Signals, 2-16, 13-5
60x processor interface
DHn/DLn, 2-19
IDSEL, 2-16
alternate functions list, 2-4
byte enable signals, 7-12
C/BEn, 7-13
CHKSTOP_IN, 2-28
clock
CKO, 2-34
clock signal description, 2-32
OSC_IN, 2-33
PCI_CLK, 2-33
PCI_SYNC_IN, 2-33
PCI_SYNC_OUT, 2-33
SDRAM_CLK, 2-33
SDRAM_SYNC_IN, 2-33
SDRAM_SYNC_OUT, 2-33
configuration pins sampled at reset, 2-38
cross-reference list, 2-4
DA, 2-30
debug address attribute signals, 15-2
debug signals, 2-29
EPIC control
EPIC signal description, 2-23, 11-2
IRQn, 2-23, 11-9
L_INT, 2-24, 11-2
S_CLK, 2-24, 11-11
S_FRAME, 2-24, 11-11
S_INT, 2-24, 11-10
S_RST, 2-24, 11-11
serial interrupt mode description, 2-24
signal summary, 11-2
HRST_CPU, 2-26, 2-26
HRST_CTRL, 2-26
2
I C interface
SCL, 2-25, 10-2
SDA, 2-25, 10-2
signal summary, 2-25, 10-2
MAA, 2-30, 15-2
memory attribute signals, 1-20
memory interface
address signal mappings, 6-5
Index Index-13