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11.9.8.3
Internal (I
11.9.8.4
Internal (I
11.9.9
Processor-Related Registers ....................................................................... 11-27
11.9.9.1
Processor Current Task Priority Register (PCTPR) ............................... 11-27
11.9.9.2
Processor Interrupt Acknowledge Register (IACK)............................... 11-27
11.9.10
Processor End-of-Interrupt Register (EOI)................................................. 11-28
12.1
Internal Buffers ................................................................................................. 12-1
12.1.1
Processor Core/Local Memory Buffers ........................................................ 12-2
12.1.2
Processor/PCI Buffers................................................................................... 12-3
12.1.2.1
Processor-to-PCI-Read Buffer (PRPRB).................................................. 12-4
12.1.2.2
Processor-to-PCI-Write Buffers (PRPWBs)............................................. 12-5
12.1.3
PCI/Local Memory Buffers .......................................................................... 12-6
12.1.3.1
PCI to Local Memory Read Buffering ..................................................... 12-7
12.1.3.1.1
12.1.3.1.2
12.1.3.2
PCI-to-Local-Memory-Write Buffers (PCMWBs)................................... 12-8
12.2
Internal Arbitration ........................................................................................... 12-9
12.2.1
Arbitration Between PCI and DMA Accesses to Local Memory................. 12-9
12.2.1.1
DMA Transaction Boundaries for Memory/Memory Transfers ............ 12-10
12.2.1.2
DMA Transaction Boundaries for Memory to PCI Transfers ................ 12-10
12.2.1.3
DMA Transaction Boundaries for PCI-Memory Transfers ................... 12-11
12.2.1.4
PCI and DMA Reads from Slow Memory/Port X.................................. 12-11
12.2.2
Internal Arbitration Priorities...................................................................... 12-11
12.2.3
Guaranteeing Minimum PCI Access Latency to Local Memory ............... 12-13
13.1
Overview........................................................................................................... 13-1
13.1.1
Error Handling Block Diagram..................................................................... 13-2
13.1.2
Priority of Externally Generated Errors and Exceptions .............................. 13-2
13.2
Exceptions and Error Signals............................................................................ 13-3
13.2.1
System Reset................................................................................................. 13-3
13.2.2
Processor Core Error Signal (mcp) .............................................................. 13-3
13.2.3
PCI Bus Error Signals................................................................................... 13-4
13.2.3.1
System Error (SERR) ............................................................................... 13-4
13.2.3.2
Parity Error (PERR).................................................................................. 13-5
13.2.3.3
Nonmaskable Interrupt (NMI) .................................................................. 13-5
xviii
CONTENTS
2
C, DMA, MU) Interrupt Vector/Priority Registers (IIVPRs) 11-26
2
C, DMA or MU) Interrupt Destination Registers (IIDRs).... 11-26
Chapter 12
Central Control Unit
PCI-to-Local-Memory-Read Buffers (PCMRBs)................................. 12-7
Speculative PCI Reads from Local Memory ........................................ 12-8
Chapter 13
Error Handling
MPC8240 Integrated Processor User's Manual
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