Pci Interface Configuration Registers; Pci Accessible Configuration Space - Motorola MPC8240 User Manual

PCI Interface Configuration Registers
.
Reserved
Class Code
BIST Control
MAX LAT
PCI Arbiter Control
Figure 4-2. PCI Accessible Configuration Space
4.2 PCI Interface Configuration Registers
The PCI Local Bus Specification defines the configuration registers from 0x00 through
0x3F. Table 4-4 summarizes the PCI configuration registers of the MPC8240. Detailed
descriptions of these registers are provided in the PCI Local Bus Specification.
Table 4-4. PCI Configuration Space Header Summary
Address
Register Name
Offset
0x00 Vendor ID
0x02 Device ID
0x04 PCI command
0x06 PCI status
0x08 Revision ID
0x09 Standard programming
interface
0x0A Subclass code
0x0B Base class code
0x0C Cache line size
0x0D Latency timer
0x0E Header type
0x0F BIST control
0x10–0x2F —
4-10
Device ID (0x0003)
PCI Status
Subclass Code
Header Type
Local Memory Base Address Register
Peripheral Control and Status Registers Base Address Register
Expansion ROM Base Address
MIN GNT
/ / / / / / / /
Identifies the manufacturer of the device (0x1057 = Motorola)
Identifies the particular device (0x0003 = MPC8240)
Provides coarse control over a device's ability to generate and respond to
PCI bus cycles (see Section 4.2.1, "PCI Command Register—Offset 0x04,"
for more information)
Records status information for PCI bus-related events (see Section 4.2.2,
"PCI Status Register—Offset 0x06," for more information)
Specifies a device-specific revision code (assigned by Motorola)
Identifies the register-level programming interface
of the MPC8240 (0x00)
Identifies more specifically the function of the MPC8240
(0x00 = host bridge)
Broadly classifies the type of function the MPC8240 performs
(0x06 = bridge device)
Specifies the system cache line size
Specifies the value of the latency timer for this bus master in PCI bus clock
units
Bits 0–6 identify the layout of bytes 10–3F; bit 7 indicates a multifunction
device. The MPC8240 uses the most common header type (0x00).
Optional register for control and status of built-in self test (BIST)
Reserved on the MPC8240
MPC8240 Integrated Processor User's Manual
Vendor ID (0x1057)
PCI Command
Standard Programming Revision ID
Latency Timer Cache Line Size
Interrupt Pin Interrupt Line
/ / / / / / / /
Description
Address
Offset (Hex)
00
04
08
0C
10
14
30
3C
40
44