Miv Signal Timing - Motorola MPC8240 User Manual

Table 15-7. Memory Interface Valid Signal Definition
Signal Name Pins
MIV 1

15.4.1 MIV Signal Timing

The MIV signal is an active low signal and has timing characteristics as shown in
Figure 15-8 through Figure 15-16.
SDRAM_CLK[0:3]
RAS/CS[0:7]
CAS/DQM[0:7]
ADDRESS
DATA
WE
DEBUG ADDRESS
MIV
MAA
NOTES:
1. Subscripts identify programmable timing variables (RP 1 , RCD 2 , CAS 3 ).
2. MIV asserts for address and control on the first clock cycle that RAS or CAS is asserted
for a read.
3. MIV asserts for data on the last clock cycle that CAS is asserted for a read.
Figure 15-8. Example FPM Debug Address, MIV, and MAA Timings for Burst Read
Active I/O
Low O Indicates that the transaction address or data is valid on
the memory bus.
RP
1
RC
CRP RCD
2
CP
CSH
ROW
ASR RAH ASC CAH
RAD
AA
RAC
VALID
Operation
Chapter 15. Debug Features
Signal Meaning
RASP
CP
4
CAS CAS
3
PC
COL COL
ASC CAH
DATA0
AA
CAC
VALID
VALID
Memory Interface Valid (MIV)
CP
4
CAS
5
5
COL
DATA0 DATA0
AA
CAC CAC
VALID
15-9