Motorola DigitalDNA ColdFire MCF5272 Manuals

Manuals and User Guides for Motorola DigitalDNA ColdFire MCF5272. We have 1 Motorola DigitalDNA ColdFire MCF5272 manual available for free PDF download: User Manual

Motorola DigitalDNA ColdFire MCF5272 User Manual

Motorola DigitalDNA ColdFire MCF5272 User Manual (550 pages)

Integrated Microprocessor

Brand: Motorola | Category: Computer Hardware | Size: 5.96 MB

Table of Contents

Table of Contents
5
Pinout
29
- Overview
  39
- Coldfire Core
  40
Chapter 1 Overview

49
- MCF5272 Key Features
  49
- MCF5272 Architecture
  52
- Version 2 Coldfire Core
  52
- System Integration Module (SIM)
  53
- External Bus Interface
  53
- Chip Select and Wait State Generation
  53
- System Configuration and Protection
  53
- Power Management
  54
- Parallel Input/Output Ports
  54
- Interrupt Inputs
  54
- UART Module
  54
- Timer Module
  55
- Test Access Port
  55
- System Design
  55
- System Bus Configuration
  55
- MCF5272-Specific Features
  56
- Physical Layer Interface Controller (PLIC)
  56
- Pulse-Width Modulation (PWM) Unit
  56
- Queued Serial Peripheral Interface (QSPI)
  56
- Universal Serial Bus (USB) Module
  57
Chapter 2 Coldfire Core

59
- Features and Enhancements
  59
- Decoupled Pipelines
  59
- Instruction Fetch Pipeline (IFP)
  60
- Operand Execution Pipeline (OEP)
  61
- Illegal Opcode Handling
  61
  - Hardware Multiply/Accumulate (MAC) Unit
    61
  - Hardware Divide Unit
    62
  - Programming Model
    63
  - User Programming Model
    64
  - Stack Pointer (A7, SP)
    65
Chapter 3

66
Chapter 4 Local Memory

97
- Local Memory Registers
  98
- SRAM Base Address Register (RAMBAR)
  99
- SRAM Initialization
  100
- Programming RAMBAR for Power Management
  101
- ROM Programming Model
  102
- Programming ROMBAR for Power Management
  103
- Instruction Cache Operation
  105
- Cacheable Accesses
  106
- Reset
  107
- Instruction Cache Programming Model
  108
- Cache Control Register (CACR)
  109
- Access Control Registers (ACR0 and ACR1)
  111
Chapter 5 Debug Support

113
- Signal Description
  114
- Begin Execution of Taken Branch (PST = 0X5)
  116
  - Programming Model
    117
  - Revision a Shared Debug Resources
    119
  - Address Breakpoint Registers (ABLR, ABHR)
    121
  - Configuration/Status Register (CSR)
    122
  - Data Breakpoint/Mask Registers (DBR, DBMR)
    123
  - Program Counter Breakpoint/Mask Registers (PBR, PBMR)
    124
  - Trigger Definition Register (TDR)
    126
  - Background Debug Mode (BDM)
    127
  - CPU Halt
    128
  - BDM Serial Interface
    129
  - Receive Packet Format
    130
  - BDM Command Set
    131
  - Coldfire BDM Command Format
    132
  - Command Sequence Diagrams
    133
  - Command Set Descriptions
    134
  - Read Memory Location (Read)
    137
  - Write Memory Location (Write)
    138
  - Real-Time Debug Support
    149
  - Theory of Operation
    150
  - Emulator Mode
    151
  - User Instruction Set
    152
  - Supervisor Instruction Set
    156
  - Motorola-Recommended BDM Pinout
    157
- System Integration Module (SIM)
  159
Chapter 7 Interrupt Controller

160
- Programming Model
  161
- Module Base Address Register (MBAR)
  162
- System Configuration Register (SCR)
  163
Chapter 9

164
- SDRAM Controller
  164
- Power Management Register (PMR)
  165
- DMA Controller Module
  166
- Overview
  185
Chapter 8

186
- Boot CS0 Operation
  186
- Chip Select Base Registers (CSBR0–CSBR7)
  187
- Chip Select Option Registers (CSOR0–CSOR7)
  189
  - Overview
    191
  - Interface to SDRAM Devices
    195
  - SDRAM Banks, Page Hits, and Page Misses
    196
  - SDRAM Registers
    197
  - SDRAM Timing Register (SDTR)
    199
  - Auto Initialization
    200
  - Performance
    201
  - Solving Timing Issues with SDCR[INV]
    203
  - SDRAM Interface
    206
  - SDRAM Read Accesses
    207
  - SDRAM Write Accesses
    209
  - SDRAM Refresh Timing
    211
Chapter 10

215
- DMA Data Transfer Types
  215
- DMA Address Modes
  216
- DMA Interrupt Register (DIR)
  218
- DMA Source Address Register (DSAR)
  219
- DMA Destination Address Register (DDAR)
  220
  - Overview
    221
  - Module Operation
    222
Chapter 11

223
- Transceiver Connection
  223
- FEC Frame Transmission
  224
- FEC Frame Reception
  225
- CAM Interface
  226
- Ethernet Address Recognition
  227
- Hash Table Algorithm
  228
- Interpacket Gap Time
  229
- Ethernet Error-Handling Procedure
  230
Chapter 12

262
Chapter 13

298
Chapter 14 Queued Serial Peripheral Interface (QSPI) Module

339
- Interface and Pins
  340
- Internal Bus Interface
  341
- Qspi Ram
  342
- Receive RAM
  343
- Transmit RAM
  344
- Transfer Delays
  345
- Transfer Length
  346
- Programming Model
  347
- QSPI Delay Register (QDLYR)
  349
- QSPI Wrap Register (QWR)
  350
- QSPI Address Register (QAR)
  352
- Programming Example
  353
- Timer Module
  355
Chapter 15

356
- Timer Operation
  356
- General-Purpose Timer Registers
  357
- Timer Reference Registers (TRR0–TRR3)
  358
- Timer Capture Registers (TCR0–TCR3)
  359
- UART Modules
  361
- Serial Module Overview
  362
- Register Descriptions
  363
- UART Mode Registers 1 (Umr1N)
  365
- UART Mode Register 2 (Umr2N)
  366
- UART Status Registers (Usrn)
  367
- UART Clock-Select Registers (Ucsrn)
  368
- UART Command Registers (Ucrn)
  369
- UART Receiver Buffers (Urbn)
  371
- UART Input Port Change Registers (Uipcrn)
  372
- UART Interrupt Status/Mask Registers (Uisrn/Uimrn)
  373
- UART Divider Upper/Lower Registers (Udun/Udln)
  374
- UART Autobaud Registers (Uabun/Uabln)
  375
- UART Receiver FIFO Registers (Urfn)
  376
- UART Fractional Precision Divider Control Registers (Ufpdn)
  377
- UART Input Port Registers (Uipn)
  378
- Operation
  380
- Calculating Baud Rates
  381
- External Clock
  382
- Transmitter and Receiver Operating Modes
  383
- Receiver
  385
- Transmitter FIFO
  386
- Looping Modes
  388
- Remote Loop-Back Mode
  389
  - Bus Operation
    391
  - UART Module Initialization Sequence
    392
- Overview
  397
Chapter 17 Port Control Registers

398
- Port B Control Register (PBCNT)
  401
- Port C Control Register
  404
- Data Direction Registers
  405
- Port a Data Direction Register (PADDR)
  406
- Port C Data Direction Register (PCDDR)
  407
- Port Data Register (Pxdat)
  408
Chapter 16

409
- Overview
  409
Chapter 18 PWM Operation

410
- PWM Control Register (Pwcrn)
  411
- PWM Width Register (Pwwdn)
  412
Chapter 19 Signal Descriptions

415
- Address Bus (A[22:0]/SDRAM_ADR[13:0])
  430
- Dynamic Data Bus Sizing
  431
- Read/Write (R/W)
  433
- Bypass
  434
- Dreseten
  435
- UART0 Module Signals and PB[4:0]
  436
- Request to Send (URT0_RTS/PB3)
  437
- USB Transmitter Output Enable (Usb_Txen/Pa5)
  438
  - Timer Module Signals
    439
  - Collision (E_COL)
    440
  - Receive Error (E_Rxer/Pb14)
    441
  - Queued Serial Peripheral Interface (QSPI) Signals
    442
  - Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS)
    443
  - Data Clock (DCL0/URT1_CLK)
    444
  - D-Channel Request(DREQ0/PA10)
    445
  - GCI/IDL Frame Sync (FSC1/FSR1/DFSC1)
    446
  - GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12)
    447
  - JTAG Test Access Port and BDM Debug Port
    448
  - Test and Debug Data in (TDI/DSI)
    449
  - Debug Data (DDATA[3:0])
    450
  - Power Supply Pins
    451
Chapter 20 Bus Operation

453
- Address Bus (A[22:0])
  454
- Transfer Acknowledge (TA)
  455
- Transfer Error Acknowledge (TEA)
  456
- Bus Characteristics
  457
- Bus Sizing
  458
- External Bus Interface Types
  462
- Interface for FLASH/SRAM Devices Without Byte Strobes
  467
- Burst Data Transfers
  472
- Interrupt Cycles
  473
- Bus Errors
  474
- Bus Arbitration
  476
- Master Reset
  477
- Normal Reset
  478
- Software Watchdog Timer Reset Operation
  479
- Soft Reset Operation
  480
Chapter 21 IEEE 1149.1 Test Access Port (JTAG)

483
- JTAG Test Access Port and BDM Debug Port
  484
- TAP Controller
  485
- Boundary Scan Register
  486
- Instruction Register
  489
- Restrictions
  490
- Non-IEEE 1149.1 Operation
  491
Chapter 22 Mechanical Data

493
- Package Dimensions
  494
Chapter 23 Electrical Characteristics

495

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