Motorola MPC8240 User Manual page 31

Table
Number
1-1 Programmable Processor Power Modes .................................................................... 1-18
1-2 Peripheral Logic Power Modes Summary ................................................................. 1-19
2-1 MPC8240 Signal Cross Reference................................................................................ 2-4
2-2 Output Signal States During System Reset................................................................... 2-7
2-3 PCI Command Encodings........................................................................................... 2-11
2-4 Memory Data Bus Byte Lane Assignments................................................................ 2-19
2-5 MPC8240 Reset Configuration Signals ...................................................................... 2-39
3-1 Address Map B-Processor View in Host Mode ......................................................... 3-2
3-2 Address Map B-PCI Memory Master View in Host Mode........................................ 3-2
3-3 Address Map B-PCI Memory Master View in Agent Mode ..................................... 3-3
3-4 Address Map B-PCI I/O Master View ....................................................................... 3-3
3-5 Address Map B-Processor View in Host Mode Options............................................ 3-8
3-6 Address Map B-PCI Memory Master View in Host Mode Options .......................... 3-9
3-7 ATU Register Summary ............................................................................................. 3-14
3-8 Bit Settings for LMBAR-0x10................................................................................. 3-15
3-9 Bit Settings for ITWR-0x0_2310............................................................................. 3-16
3-10 Bit Settings for OMBAR-0x0_2300 ........................................................................ 3-17
3-11 Bit Settings for OTWR-0x0_2308 ........................................................................... 3-17
3-12 Embedded Utilities Local Memory Register Summary.............................................. 3-19
3-13 Embedded Utilities Peripheral Control and Status Register Summary ...................... 3-20
4-1 Internal Register Access Port Locations ....................................................................... 4-1
4-2 MPC8240 Configuration Registers Accessible from the Processor Core .................... 4-5
4-3 MPC8240 Configuration Registers Accessible from the PCI Bus ............................... 4-9
4-4 PCI Configuration Space Header Summary ............................................................... 4-10
4-5 Bit Settings for PCI Command Register-0x04......................................................... 4-12
4-6 Bit Settings for PCI Status Register-0x06................................................................ 4-13
4-7 Programming Interface-0x09 ................................................................................... 4-14
4-8 PCI Base Class Code-0x0B...................................................................................... 4-14
4-9 Cache Line Size Register-0x0C ............................................................................... 4-14
4-10 Latency Timer Register-0x0D.................................................................................. 4-14
4-11 Local Memory Base Address Register Bit Definitions-0x10................................... 4-15
4-12 PCSR Base Address Register Bit Definitions-0x14................................................. 4-15
4-13 Interrupt Line Register-0x3C ................................................................................... 4-16
4-14 PCI Arbiter Control Register Bit Definitions-0x46 ................................................. 4-16
4-15 Bit Settings for Power Management Configuration Register 1-0x70 ...................... 4-17
4-16 Power Management Configuration Register 2-0x72................................................ 4-19
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Tables
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