Motorola MPC8240 User Manual page 25

Figure
Number
6-17 SDRAM Refresh Period ............................................................................................. 6-31
6-18 SDRAM Bank Staggered CBR Refresh Timing......................................................... 6-33
6-19 SDRAM Self Refresh Entry........................................................................................ 6-35
6-20 SDRAM Self Refresh Exit.......................................................................................... 6-35
6-21 Processor Burst Reads from SDRAM......................................................................... 6-37
6-22 Processor Single-Beat Reads from SDRAM .............................................................. 6-38
6-23 Processor Burst Writes to SDRAM ............................................................................ 6-39
6-24 Processor Single-Beat Writes to SDRAM .................................................................. 6-40
6-25 Processor Single-Beat Reads followed by Writes to SDRAM ................................... 6-41
6-26 PCI Reads from SDRAM-Speculative Reads Enabled............................................... 6-43
6-27 PCI Reads from SDRAM-Speculative Reads Disabled.............................................. 6-44
6-28 PCI Writes to SDRAM ............................................................................................... 6-45
6-29 FPM or EDO DRAM Memory Interface Block Diagram .......................................... 6-46
6-30 Example 16-Mbyte DRAM System with Parity-64-Bit Mode................................. 6-47
6-31 DRAM Memory Organization.................................................................................... 6-48
6-32 DRAM Address Multiplexing SDMA[12:0]-32 Bit Mode ...................................... 6-52
6-33 DRAM Address Multiplexing SDMA[12:0]-64 Bit Mode ...................................... 6-53
6-34 FPM-EDO Flow-through Memory Interface .............................................................. 6-55
6-35 DRAM Single-Beat Read Timing (No ECC) ............................................................. 6-58
6-36 DRAM Four-Beat Burst Read Timing (No ECC)-64-Bit Mode.............................. 6-58
6-37 DRAM Eight-Beat Burst Read Timing Configuration-32-Bit Mode....................... 6-59
6-38 DRAM Single-Beat Write Timing (No ECC) ............................................................ 6-59
6-39 DRAM Four-Beat Burst Write Timing (No ECC)-64-Bit Mode............................. 6-60
6-40 DRAM Eight-beat Burst Write Timing (No ECC)-32 Bit Mode............................. 6-60
6-41 FPM DRAM Burst Read with ECC............................................................................ 6-65
6-42 EDO DRAM Burst Read Timing with ECC............................................................... 6-65
6-43 DRAM Single-Beat Write Timing with RMW or ECC Enabled ............................... 6-66
6-44 DRAM Bank Staggered CBR Refresh Timing Configuration ................................... 6-67
6-45 DRAM Self-Refresh Timing Configuration ............................................................... 6-68
6-46 PCI Reads from DRAM-Speculative Reads Enabled................................................. 6-70
6-47 PCI Reads from DRAM-Speculative Reads Disabled................................................ 6-71
6-48 PCI Writes to DRAM.................................................................................................. 6-72
6-49 ROM Memory Interface Block Diagram.................................................................... 6-73
6-50 16-Mbyte ROM System Including Parity Paths to DRAM-64-Bit Mode................ 6-74
6-51 2-Mbyte Flash Memory System Including Parity Paths to DRAM-8-Bit Mode ..... 6-75
6-52 ROM/Flash Address Multiplexing-8-Bit Mode ....................................................... 6-77
6-53 ROM/Flash Address Multiplexing-32-Bit Mode ..................................................... 6-78
6-54 ROM/Flash Address Multiplexing-64-Bit Mode ..................................................... 6-78
6-55 Read Access Timing for Non-Burst ROM/Flash Devices in 32- or 64-Bit Mode...... 6-80
6-56 Read Access Timing (Cache Block) for Burst ROM/Flash Devices in 64-Bit Mode 6-80
6-57 Read Access Timing (Cache Block) for Burst ROM/Flash Devices in 32-Bit Mode 6-81
6-58 8-Bit ROM/Flash Interface-Single-Byte Read Timing ............................................ 6-82
6-59 8-Bit ROM/Flash Interface-Two-Byte Read Timing ............................................... 6-82
ILLUSTRATIONS
Title
Illustrations
Page
Number
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