B.1 Byte Ordering Overview - Motorola MPC8240 User Manual

Appendix B
Bit and Byte Ordering
The MPC8240 supports two byte-ordering conventions for the PCI bus and local
memory—big-endian and little-endian. This appendix describes both modes and provides
examples of each. Chapter 3, "Operand Conventions," in PowerPC Microprocessor Family:
The Programming Environments for 32-bit Microprocessors, provides a general overview
of byte ordering and describes byte ordering for PowerPC microprocessors.

B.1 Byte Ordering Overview

For big-endian data, the MSB is stored at the lowest (or starting) address and the LSB at the
highest (or ending) address. This is called big-endian because the big (most-significant) end
of the scalar comes first in memory.
For true little-endian byte ordering, the LSB is stored at the lowest address and the MSB at
the highest address. This is called true little-endian because the little (least-significant) end
of the scalar comes first in memory.
For PowerPC little-endian byte ordering (also referred to as munged little-endian), the
address of data is modified so that the memory structure appears to be little-endian to the
executing processor when, in fact, the byte ordering is big-endian. The address modification
is called munging. Note that the term 'munging' is not defined or used in the PowerPC
architecture specification but is commonly used to describe address modifications. The byte
ordering is called PowerPC little-endian because PowerPC microprocessors use this
method to operate in little-endian mode.
In addition, the PCI bus uses a bit format where the most-significant bit (msb) for data is
AD31, while the processor core and the internal peripheral logic data bus use a bit format
where the msb is DH0. Thus, PCI data bit AD31 equates to the processor's data bits DH0
and DL0, while PCI data bit AD0 equates to the processor's data bits DH31 and DL31.
B.2 Byte-Ordering Mechanisms
The byte-ordering mechanisms in the MPC8240 are controlled by programmable
parameters. The PowerPC architecture defines two bits in a processor's machine state
register (MSR) for specifying byte ordering—LE (little-endian mode) and ILE (exception
little-endian mode). For the MPC8240, these bits control only the addresses generated by
Appendix B. Bit and Byte Ordering B-1