Address Map B—Processor View In Host Mode Options - Motorola MPC8240 User Manual

Address Map B Options
Table 3-5. Address Map B—Processor View in Host Mode Options
Processor Core Address Range
Hex
0000_0000 0009_FFFF
000A_0000 000F_FFFF
0010_0000 3FFF_FFFF
8000_0000 FCFF_FFFF
FD00_0000 FDFF_FFFF
FE00_0000 FE7F_FFFF
1. This address range is separately programmable (see Section 4.9, "Address Map B Options Register—0xE0")
for the processor interface and the PCI interface to control whether accesses to this address range go to local
memory or PCI memory.
2. If AMBOR[CPU_FD_ALIAS_EN] = 1 (see Section 4.9, "Address Map B Options Register—0xE0"), the
MPC8240 forwards processor transactions in this range to the zero-based PCI memory space with the 8 most
significant bits cleared (that is, AD[31:0] = 0x00 || A[8:31] of the internal peripheral logic address bus).
3. Processor addresses are translated to PCI addresses as follows:
PCI address (AD[31:0]) = 0x00 || A[8:31] to generate the address range 0000_0000–007F_FFFF. Note that
only 64 Kbytes has been defined (0xFE00_0000–0xFE00–FFFF). The processor address range
0xFE01_0000–0xFE7F_FFFF is reserved for future use.
Figure 3-4 shows the optional processor compatibility hole and processor alias space in
map B.
3-8
Decimal
0 640K - 1
640K 1M - 1
1M 1G - 1
2G 4G - 48M - 1
4G - 48M 4G - 32M - 1
4G - 32M 4G - 32M +
64K - 1
MPC8240 Integrated Processor User's Manual
PCI Address Range
No PCI cycle
000A_0000–000F_FFFF
No PCI cycle
8000_0000–FCFF_FFFF
0000_0000–00FF_FFFF
0000_0000–0000_FFFF
Definition
Local memory space
1
Compatibility hole
Local memory space
PCI memory space
PCI memory space
2
(16 Mbytes), 0-based
PCI I/O space
3
(8 Mbytes), 0-based