Ras Encoding - Motorola MPC8240 User Manual

Encoded version of RAS[0:7]
0 0
31 30 29 27 26
Figure 15-4. 32-Bit Mode, DRAM and SDRAM Physical Address for Debug
1 1 1 1 1 1 1 1
31 30 29 30 27 26 25 24 23
Figure 15-5. 64-Bit Mode, ROM and Flash Physical Address for Debug
1 1 1 1 1 1 1 1
31 30 29 30 27 26 25 24 23
Figure 15-6. 32-Bit Mode, ROM and Flash Physical Address for Debug
1 1 1 1 1 1 1 1
31 30 29 30 27 26 25 24 23
Figure 15-7. 8-Bit Mode, ROM and Flash Physical Address for Debug

15.3.4 RAS Encoding

The encoding of RAS/CS[0:7] to form bits 29–27 of the physical address for DRAM and
SDRAM transactions is based on the memory bank configuration as programmed in the
bank starting and ending address configuration registers located at offsets 0x80, 0x84,
0x88, 0x8C, 0x90, 0x94, 0x98, and 0x9C. For this encoding algorithm to be deterministic,
DRAM and SDRAM banks are not allowed to cross a 128-Mbyte address partition (that is,
the starting and ending address for any one bank must fall within the same 128-Mbyte
partition). Obviously, such RAS information is relevant only for DRAM (and SDRAM) and
not for ROM/Flash. For a simple example of RAS encodings, see Table 15-6 below.
DA[15:0]
DA[12:0]
DA[12:0]
DA[12:0]
Chapter 15. Debug Features
Memory Debug Address
SDMA[8:0] of column address
11 10 3
AR[7:0] of address
11 10 3
AR[8:0] of address
11 10
AR[10:0] of address
11 10
Reserved
0 0
2 1 0
Reserved
0 0 0
2 1 0
Reserved
0 0
2 1 0
Reserved
0
15-7