Motorola MPC8240 User Manual page 632

PCI memory space, B-9
LMBAR (local memory base address)
register, 3-15, 4-15
Load/store
byte-reverse instructions, D-22
floating-point load instructions, D-23
floating-point move instructions, D-23
floating-point store instructions, D-23
integer load instructions, D-21
integer store instructions, D-21
load/store multiple instructions, D-22
memory synchronization instructions, D-22
string instructions, D-22
Local processor control and status registers, see
EUMB registers, 3-18
LOCK (lock) signal, 2-13, 7-29
M
MAA (memory address attribute) signals, 2-30, 15-2
Master-abort termination, PCI, 7-17
Master-abort, PCI, 13-10
MCCRn (memory control configuration)
registers, 4-42–4-49
MCP (machine check) signal, 2-27
Memory
agent mode
PCI address translation, 7-34
Memory data path error capture monitor registers
description, 15-19
Memory data path error injection/capture, 15-17
Memory interface
address signal mappings, 6-5
block diagram, 6-3
configuration registers, see Registers, memory in-
terface
DMA burst wrap, 6-61
ECC error, 13-8
EDO DRAM interface, 6-46
errors within a nibble, 13-8
features list, 1-12
Flash interface, 6-73
Flash write error, 13-7
FPM interface, 6-46
memory attribute signals, 1-20
overview, 1-13, 6-1
parity, 6-15
physical memory, 13-9
Port X, 6-89
read data parity error, 13-8
refresh overflow error, 13-9
ROM interface, 6-73
SDRAM interface, 6-6
select error, 13-9
signal summary, 6-3
Index-8
INDEX
MPC8240 Integrated Processor User's Manual
signals, see Signals, 2-16
system memory, 13-8
Memory management unit (MMU), 5-8, 5-30
Memory synchronization instructions, D-22
Message registers, see Registers
Message unit, 1-15
doorbell registers
ODBR (outbound door bell) register, 9-2
I O interface
2
hardware registers, 9-5
IFHPR, 9-15
IFQPR, 9-11
IFTPR, 9-16
IMIMR, 9-14
IMISR, 9-12
inbound FIFOs, 9-7
IPHPR, 9-16
IPTPR, 9-17
MUCR, 9-20
OFHPR, 9-18
OFQPR, 9-12
OFTPR, 9-18
OMIMR, 9-10
OMISR, 9-9
OPHPR, 9-19
OPTPR, 9-19
outbound free_list FIFO, 9-8
overview, 9-1
PCI configuration identification, 9-5
QBAR, 9-21
register summary, 9-5
specification, 1-16
MICRn (memory interface configuration)
registers, 4-23
MIV (memory interface valid), 2-31
MIV (memory interface valid) signal, 1-20, 15-8
Modes
cache wrap mode, 7-12
DMA controller
chaining mode, 8-5
direct mode, 8-4
doze mode, 1-18
full-power mode, 1-18
nap mode, 1-18
PCI modes
agent mode, 3-3, 7-34
host mode, 7-34
processor view in host mode, 3-2, 3-8
SDRAM register DIMM mode, 6-29
sleep mode, 1-18
MPC8240
aligned scalars, address modification, B-6
MPC8240 as PCI bus master, 7-2
MPC8240 as PCI target, 7-3