Epic Block Diagram - Motorola MPC8240 User Manual

Table 11-1. EPIC Interface Signal Description (Continued)
Signal Name Pins
IRQ3/S_FRAME
IRQ4/L_INT

11.1.3 EPIC Block Diagram

The EPIC unit in the MPC8240 is accessible from the processor only. The processor reads
and writes the configuration and status registers of EPIC. These registers are memory
mapped.
The following block diagram shows the EPIC unit and its relationship to the processor core
and external signals:
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
I/O
1 I/O Direct IRQ mode—Input representing an incoming interrupt request
Serial IRQ mode—Output that pulses low each time the interrupt
controller is sampling interrupt source 0.
1 I/O Direct IRQ mode—Input representing an incoming interrupt request
Serial IRQ mode—Not used.
Pass-through mode: output active low whenever there is an interrupt from
MPC8240's internal dma0, dma1, MU, or I
MPC8240
Processor Core
EPIC Unit
EPIC
EPIC
to
2
DMA, I C,
Controller
and MU
Interface
Figure 11-1. EPIC Unit Block Diagram
EPIC Unit Overview
State Meaning
2
C units.
External Interrupt Sources
IRQ0 / S_INT
IRQ1 / S_CLK
IRQ2 / S_RST
IRQ3/S_FRAME
IRQ4/L_INT
11-3